[PATCH 5/5] drm/mediatek: Add eDP phy driver for mt8196

[Vinod Koul]

On 18-04-25, 14:52, Bincai Liu wrote:
> Add code to support eDP phy for mt8196.

Why is the patch title not "phy: add eDP phy...." why is this tagged
drm? 

> 
> Signed-off-by: Bincai Liu <bincai.liu at mediatek.com>
> ---
>  drivers/phy/mediatek/Makefile      |   1 +
>  drivers/phy/mediatek/phy-mtk-edp.c | 262 +++++++++++++++++++++++++++++
>  2 files changed, 263 insertions(+)
>  create mode 100644 drivers/phy/mediatek/phy-mtk-edp.c
> 
> diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile
> index 1b8088df71e8..49d9ea42497a 100644
> --- a/drivers/phy/mediatek/Makefile
> +++ b/drivers/phy/mediatek/Makefile
> @@ -4,6 +4,7 @@
>  #
>  
>  obj-$(CONFIG_PHY_MTK_DP)		+= phy-mtk-dp.o
> +obj-$(CONFIG_PHY_MTK_DP)		+= phy-mtk-edp.o
>  obj-$(CONFIG_PHY_MTK_PCIE)		+= phy-mtk-pcie.o
>  obj-$(CONFIG_PHY_MTK_TPHY)		+= phy-mtk-tphy.o
>  obj-$(CONFIG_PHY_MTK_UFS)		+= phy-mtk-ufs.o
> diff --git a/drivers/phy/mediatek/phy-mtk-edp.c b/drivers/phy/mediatek/phy-mtk-edp.c
> new file mode 100644
> index 000000000000..fadcbda55b70
> --- /dev/null
> +++ b/drivers/phy/mediatek/phy-mtk-edp.c
> @@ -0,0 +1,262 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019-2022 MediaTek Inc.
> + * Copyright (c) 2022 BayLibre
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#define PHYD_OFFSET			0x0000
> +#define PHYD_DIG_LAN0_OFFSET		0x1000
> +#define PHYD_DIG_LAN1_OFFSET		0x1100
> +#define PHYD_DIG_LAN2_OFFSET		0x1200
> +#define PHYD_DIG_LAN3_OFFSET		0x1300
> +#define PHYD_DIG_GLB_OFFSET		0x1400
> +
> +#define DP_PHY_DIG_PLL_CTL_0		(PHYD_DIG_GLB_OFFSET + 0x10)
> +#define FORCE_PWORE_STATE_FLDMASK		GENMASK(2, 0)
> +#define FORCE_PWORE_STATE_VALUE			0x7
> +
> +#define IPMUX_CONTROL			(PHYD_DIG_GLB_OFFSET + 0x98)
> +#define EDPTX_DSI_PHYD_SEL_FLDMASK		0x1
> +#define EDPTX_DSI_PHYD_SEL_FLDMASK_POS		0
> +
> +#define DP_PHY_DIG_TX_CTL_0		(PHYD_DIG_GLB_OFFSET + 0x74)
> +#define TX_LN_EN_FLDMASK			0xf
> +
> +#define mtk_edp_PHY_DIG_PLL_CTL_1	(PHYD_DIG_GLB_OFFSET + 0x14)
> +#define TPLL_SSC_EN				BIT(8)
> +
> +#define mtk_edp_PHY_DIG_BIT_RATE		(PHYD_DIG_GLB_OFFSET + 0x3C)
> +#define BIT_RATE_RBR				0x1
> +#define BIT_RATE_HBR				0x4
> +#define BIT_RATE_HBR2				0x7
> +#define BIT_RATE_HBR3				0x9
> +
> +#define mtk_edp_PHY_DIG_SW_RST		(PHYD_DIG_GLB_OFFSET + 0x38)
> +#define DP_GLB_SW_RST_PHYD			BIT(0)
> +#define DP_GLB_SW_RST_PHYD_MASK			BIT(0)
> +
> +#define DRIVING_FORCE			0x30
> +#define EDP_TX_LN_VOLT_SWING_VAL_FLDMASK	0x6
> +#define EDP_TX_LN_VOLT_SWING_VAL_FLDMASK_POS	1
> +#define EDP_TX_LN_PRE_EMPH_VAL_FLDMASK		0x18
> +#define EDP_TX_LN_PRE_EMPH_VAL_FLDMASK_POS	3
> +
> +struct mtk_edp_phy {
> +	struct regmap *regs;
> +};
> +
> +enum DPTX_LANE_NUM {
> +	DPTX_LANE0 = 0x0,
> +	DPTX_LANE1 = 0x1,
> +	DPTX_LANE2 = 0x2,
> +	DPTX_LANE3 = 0x3,
> +	DPTX_LANE_MAX,
> +};
> +
> +enum DPTX_LANE_COUNT {
> +	DPTX_LANE_COUNT1 = 0x1,
> +	DPTX_LANE_COUNT2 = 0x2,
> +	DPTX_LANE_COUNT4 = 0x4,
> +};
> +
> +static void mtk_edptx_phyd_reset_swing_pre(struct mtk_edp_phy *edp_phy)
> +{
> +	regmap_update_bits(edp_phy->regs, PHYD_DIG_LAN0_OFFSET + DRIVING_FORCE,
> +			   EDP_TX_LN_VOLT_SWING_VAL_FLDMASK |
> +			   EDP_TX_LN_PRE_EMPH_VAL_FLDMASK, 0x0);
> +	regmap_update_bits(edp_phy->regs, PHYD_DIG_LAN1_OFFSET + DRIVING_FORCE,
> +			   EDP_TX_LN_VOLT_SWING_VAL_FLDMASK |
> +			   EDP_TX_LN_PRE_EMPH_VAL_FLDMASK, 0x0);
> +	regmap_update_bits(edp_phy->regs, PHYD_DIG_LAN2_OFFSET + DRIVING_FORCE,
> +			   EDP_TX_LN_VOLT_SWING_VAL_FLDMASK |
> +			   EDP_TX_LN_PRE_EMPH_VAL_FLDMASK, 0x0);
> +	regmap_update_bits(edp_phy->regs, PHYD_DIG_LAN3_OFFSET + DRIVING_FORCE,
> +			   EDP_TX_LN_VOLT_SWING_VAL_FLDMASK |
> +			   EDP_TX_LN_PRE_EMPH_VAL_FLDMASK, 0x0);
> +}
> +
> +static int mtk_edp_phy_init(struct phy *phy)
> +{
> +	struct mtk_edp_phy *edp_phy = phy_get_drvdata(phy);
> +
> +	regmap_update_bits(edp_phy->regs, IPMUX_CONTROL, 0,
> +			   EDPTX_DSI_PHYD_SEL_FLDMASK);
> +
> +	regmap_update_bits(edp_phy->regs, DP_PHY_DIG_PLL_CTL_0,
> +			   FORCE_PWORE_STATE_VALUE,
> +			   FORCE_PWORE_STATE_FLDMASK);
> +
> +	return 0;

consider making this void return type

-- 
~Vinod