[v3,1/2] dt-bindings: memory-controllers: Add MediaTek DRAM controller interface

[Crystal Guo (郭晶)]

On Wed, 2025-03-26 at 11:18 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
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> 
> 
> Il 26/03/25 07:30, Crystal Guo ha scritto:
> > A MediaTek DRAM controller interface to provide the current DDR
> > data rate.
> > 
> > Signed-off-by: Crystal Guo <crystal.guo at mediatek.com>
> > ---
> >   .../memory-controllers/mediatek,dramc.yaml    | 44
> > +++++++++++++++++++
> >   1 file changed, 44 insertions(+)
> >   create mode 100644 Documentation/devicetree/bindings/memory-
> > controllers/mediatek,dramc.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/memory-
> > controllers/mediatek,dramc.yaml
> > b/Documentation/devicetree/bindings/memory-
> > controllers/mediatek,dramc.yaml
> > new file mode 100644
> > index 000000000000..8bdacfc36cb5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/memory-
> > controllers/mediatek,dramc.yaml
> 
> The filename should be "mediatek,mt8196-dramc.yaml"
> 

For other MediaTek SOCs, the method of calculating current ddr data
rate is similar to that of MT8196. After changing "mediatek,dramc.yaml"
to "mediatek,mt8196-dramc.yaml", would future Mediatek SOCs need to add
a separate yaml file again? or could they reuse mediatek,mt8196-
dramc.yaml? Thank you for your guidance.

Best regards,
Crystal

> 
> > @@ -0,0 +1,44 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2025 MediaTek Inc.
> > +%YAML 1.2
> > +---
> > +$id: 
> > https://urldefense.com/v3/__http://devicetree.org/schemas/memory-controllers/mediatek,dramc.yaml*__;Iw!!CTRNKA9wMg0ARbw!gH5hMTJ34ZcYfNMfLUNL-dH9SMyQGr06kJ4jij1anezByF7IBOSbkYNdqysgHoz-rSRNwM9r6RaaTC1MO2882ojif26oaBzg$
> > +$schema: 
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!gH5hMTJ34ZcYfNMfLUNL-dH9SMyQGr06kJ4jij1anezByF7IBOSbkYNdqysgHoz-rSRNwM9r6RaaTC1MO2882ojifw8f6sUH$
> > +
> > +title: MediaTek DRAM Controller (DRAMC)
> > +
> > +maintainers:
> > +  - Crystal Guo <crystal.guo at mediatek.com>
> > +
> > +description:
> > +  A MediaTek DRAM controller interface to provide the current data
> > rate of DRAM.
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - mediatek,mt8196-dramc
> 
> P.S.: bindings maintainers: this driver is expected to get more
> compatibles soon.
> 
> Cheers,
> Angelo
> 
> 
> > +
> > +  reg:
> > +    items:
> > +      - description: anaphy registers
> > +      - description: ddrphy registers
> > +
> > +additionalProperties: false
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +
> > +examples:
> > +  - |
> > +    soc {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        memory-controller at 10236000 {
> > +            compatible = "mediatek,mt8196-dramc";
> > +            reg = <0 0x10236000 0 0x2000>,
> > +                  <0 0x10238000 0 0x2000>;
> > +        };
> > +    };
> 
>