[PATCH v3 2/2] PCI: mediatek-gen3: Add support for restricting link width

[Fei Shao]

On Wed, Sep 18, 2024 at 4:13 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno at collabora.com> wrote:
>
> Add support for restricting the port's link width by specifying
> the num-lanes devicetree property in the PCIe node.
>
> The setting is done in the GEN_SETTINGS register (in the driver
> named as PCIE_SETTING_REG), where each set bit in [11:8] activates
> a set of lanes (from bits 11 to 8 respectively, x16/x8/x4/x2).
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

Reviewed-by: Fei Shao <fshao at chromium.org>