[PATCH v2 2/9] arm64: dts: mediatek: mt8188: Add PCIe nodes

[Macpaul Lin]

On 10/3/24 14:59, Fei Shao wrote:
> 	
> 
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> Add PCIe node and the associated PHY node.
> Individual board device tree should enable the nodes as needed.
> 
> Signed-off-by: Fei Shao <fshao at chromium.org>
> ---
> 
> Changes in v2:
> - add linux,pci-domain to PCIe node
> - add power domain to PCIe PHY node.
>    The binding patch:
>    https://lore.kernel.org/all/20240926101804.22471-1-macpaul.lin@mediatek.com/
> 
>   arch/arm64/boot/dts/mediatek/mt8188.dtsi | 64 ++++++++++++++++++++++++
>   1 file changed, 64 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> index 10195a4e4e9d..23101d316c4e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -1763,6 +1763,54 @@ xhci0: usb at 112b0000 {
>   			status = "disabled";
>   		};
>   
> +		pcie: pcie at 112f0000 {
> +			compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie";
> +			reg = <0 0x112f0000 0 0x2000>;
> +			reg-names = "pcie-mac";
> +			ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>;
> +			bus-range = <0 0xff>;
> +			device_type = "pci";
> +			linux,pci-domain = <0>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +
> +			clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
> +				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
> +				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
> +				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
> +				 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
> +				 <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>;
> +			clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k",
> +				      "peri_26m", "peri_mem";
> +
> +			#interrupt-cells = <1>;
> +			interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
> +			interrupt-map = <0 0 0 1 &pcie_intc 0>,
> +					<0 0 0 2 &pcie_intc 1>,
> +					<0 0 0 3 &pcie_intc 2>,
> +					<0 0 0 4 &pcie_intc 3>;
> +			interrupt-map-mask = <0 0 0 7>;
> +
> +			iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>;
> +			iommu-map-mask = <0>;
> +
> +			phys = <&pcieport PHY_TYPE_PCIE>;
> +			phy-names = "pcie-phy";
> +
> +			power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>;
> +
> +			resets = <&watchdog MT8188_TOPRGU_PCIE_SW_RST>;
> +			reset-names = "mac";
> +
> +			status = "disabled";
> +
> +			pcie_intc: interrupt-controller {
> +				#address-cells = <0>;
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +			};
> +		};
> +
>   		nor_flash: spi at 1132c000 {
>   			compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor";
>   			reg = <0 0x1132c000 0 0x1000>;
> @@ -1775,6 +1823,22 @@ nor_flash: spi at 1132c000 {
>   			status = "disabled";
>   		};
>   
> +		pciephy: t-phy at 11c20700 {
> +			compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3";
> +			ranges = <0 0 0x11c20700 0x700>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>;
> +			status = "disabled";
> +
> +			pcieport: pcie-phy at 0 {
> +				reg = <0 0x700>;
> +				clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>;
> +				clock-names = "ref";
> +				#phy-cells = <1>;
> +			};
> +		};
> +
>   		i2c1: i2c at 11e00000 {
>   			compatible = "mediatek,mt8188-i2c";
>   			reg = <0 0x11e00000 0 0x1000>,

Reviewed-by: Macpaul Lin <macpaul.lin at mediatek.com>

Thanks.
Macpaul Lin