[RFC v1 14/14] arm64: dts: mediatek: mt7988: add operating-points

[AngeloGioacchino Del Regno]

Il 29/10/24 11:39, Frank Wunderlich ha scritto:
> From: Frank Wunderlich <frank-w at public-files.de>
> 
> Add operating points defining frequency/voltages of cpu cores.
> 
> Signed-off-by: Frank Wunderlich <frank-w at public-files.de>
> ---
>   arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 45 +++++++++++++++++++++--
>   1 file changed, 41 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> index e037854666c1..25669d498617 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
> @@ -16,32 +16,69 @@ cpus {
>   		#address-cells = <1>;
>   		#size-cells = <0>;
>   
> -		cpu at 0 {
> +		cpu0: cpu at 0 {

Where are those cpuX labels used? I don't see any usage.

>   			compatible = "arm,cortex-a73";
>   			reg = <0x0>;
>   			device_type = "cpu";
>   			enable-method = "psci";
> +			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
> +				 <&topckgen CLK_TOP_XTAL>;
> +			clock-names = "cpu", "intermediate";
> +			operating-points-v2 = <&cluster0_opp>;
>   		};
>   
> -		cpu at 1 {
> +		cpu1: cpu at 1 {
>   			compatible = "arm,cortex-a73";
>   			reg = <0x1>;
>   			device_type = "cpu";
>   			enable-method = "psci";
> +			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
> +				 <&topckgen CLK_TOP_XTAL>;
> +			clock-names = "cpu", "intermediate";
> +			operating-points-v2 = <&cluster0_opp>;
>   		};
>   
> -		cpu at 2 {
> +		cpu2: cpu at 2 {
>   			compatible = "arm,cortex-a73";
>   			reg = <0x2>;
>   			device_type = "cpu";
>   			enable-method = "psci";
> +			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
> +				 <&topckgen CLK_TOP_XTAL>;
> +			clock-names = "cpu", "intermediate";
> +			operating-points-v2 = <&cluster0_opp>;
>   		};
>   
> -		cpu at 3 {
> +		cpu3: cpu at 3 {
>   			compatible = "arm,cortex-a73";
>   			reg = <0x3>;
>   			device_type = "cpu";
>   			enable-method = "psci";
> +			clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
> +				 <&topckgen CLK_TOP_XTAL>;
> +			clock-names = "cpu", "intermediate";
> +			operating-points-v2 = <&cluster0_opp>;
> +		};
> +
> +		cluster0_opp: opp-table-0 {
> +			compatible = "operating-points-v2";
> +			opp-shared;
> +			opp00 {

...But you can also be consistent with other devicetrees and follow the pattern
for the node names of the OPP entries.

opp-800000000
opp-1100000000
...etc

Cheers,
Angelo

> +				opp-hz = /bits/ 64 <800000000>;
> +				opp-microvolt = <850000>;
> +			};
> +			opp01 {
> +				opp-hz = /bits/ 64 <1100000000>;
> +				opp-microvolt = <850000>;
> +			};
> +			opp02 {
> +				opp-hz = /bits/ 64 <1500000000>;
> +				opp-microvolt = <850000>;
> +			};
> +			opp03 {
> +				opp-hz = /bits/ 64 <1800000000>;
> +				opp-microvolt = <900000>;
> +			};
>   		};
>   	};
>