[PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device

[CK Hu (胡俊光)]

Hi, Shu-hsiang:

On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> 1. Add camera isp7x module device document
> 2. Add camera interface device document
> 
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang at mediatek.com>
> ---

[snip]

> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPnhKvzWQ$ 
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jkHmqtxOst6Dv88RaE-ss9VaxKxFo4FuPl1smXTEnkiijU7jS9nkYGBPoLr8g4Ji2dZpb_7LHWrLpIyu2qoPfKVBdTw$ 
> +
> +title: The cam-raw unit of MediaTek ISP system
> +
> +maintainers:
> +  - Shu-hsiang Yang <shu-hsiang.yang at mediatek.com>
> +  - Shun-yi Wang <shun-yi.wang at mediatek.com>
> +  - Teddy Chen <teddy.chen at mediatek.com>
> +
> +description:
> +  MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC.
> +
> +properties:
> +  compatible:
> +    const: mediatek,cam-raw
> +
> +  "#address-cells":
> +    const: 2
> +
> +  "#size-cells":
> +    const: 2
> +
> +  reg:
> +    items:
> +      minItems: 2
> +      maxItems: 4
> +    minItems: 1
> +    maxItems: 2
> +
> +  reg-names:
> +    minItems: 1
> +    maxItems: 2
> +
> +  mediatek,cam-id:
> +    description:
> +      Describes the index of MediaTek cam-raw unit for ISP
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1, 2]
> +
> +  mediatek,larbs:
> +    description:
> +      Describes MediaTek bus infrastructure unit for ISP system.
> +      List of phandle to the local arbiters in the current SoCs.
> +      Refer to bindings/memory-controllers/mediatek,smi-larb.yaml.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    minItems: 1
> +    maxItems: 32
> +
> +  interrupts:
> +    minItems: 1
> +
> +  dma-ranges:
> +    description:
> +      Describes the address information of IOMMU mapping to memory.
> +      Defines six fields for the MediaTek IOMMU extended iova, pa, and size.
> +    minItems: 1
> +
> +  power-domains:
> +    minItems: 1
> +
> +  clocks:
> +    minItems: 4
> +    maxItems: 16
> +
> +  clock-names:
> +    minItems: 4
> +    maxItems: 16
> +
> +  assigned-clocks:
> +    maxItems: 1
> +
> +  assigned-clock-parents:
> +    maxItems: 1
> +
> +  iommus:
> +    description:
> +      Points to the respective IOMMU block with master port as argument, see
> +      Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> +      Ports are according to the HW.
> +    minItems: 1
> +    maxItems: 32
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - interrupts
> +  - power-domains
> +  - clocks
> +  - clock-names
> +  - iommus
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/power/mediatek,mt8188-power.h>
> +    #include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +    #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
> +
> +    soc {
> +      #address-cells = <2>;
> +      #size-cells = <2>;
> +
> +      cam_raw_a at 16030000 {
> +        compatible = "mediatek,cam-raw";
> +        reg = <0 0x16030000 0 0x8000>,
> +              <0 0x16038000 0 0x8000>;

It could be

reg = <0 0x16030000 0 0x10000>;

Why do you break it into two part?

> +        reg-names = "base", "inner_base";
> +        mediatek,cam-id = <0>;
> +        mediatek,larbs = <&larb16a>;

larb information is inside iommu device, so it's not necessary to have a larb property here.

Regards,
CK

> +        interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +        dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>;
> +        power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>;
> +        clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
> +            <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
> +            <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>,
> +            <&camsys CLK_CAM_MAIN_CAM>,
> +            <&camsys CLK_CAM_MAIN_CAMTG>,
> +            <&camsys_rawa CLK_CAM_RAWA_LARBX>,
> +            <&camsys_rawa CLK_CAM_RAWA_CAM>,
> +            <&camsys_rawa CLK_CAM_RAWA_CAMTG>,
> +            <&topckgen CLK_TOP_CAM>,
> +            <&topckgen CLK_TOP_CAMTG>,
> +            <&topckgen CLK_TOP_CAMTM>;
> +        clock-names = "camsys_cam2mm0_cgpdn",
> +            "camsys_cam2mm1_cgpdn",
> +            "camsys_cam2sys_cgpdn",
> +            "camsys_cam_cgpdn",
> +            "camsys_camtg_cgpdn",
> +            "camsys_rawa_larbx_cgpdn",
> +            "camsys_rawa_cam_cgpdn",
> +            "camsys_rawa_camtg_cgpdn",
> +            "topckgen_top_cam",
> +            "topckgen_top_camtg",
> +            "topckgen_top_camtm";
> +        assigned-clocks = <&topckgen CLK_TOP_CAM>;
> +        assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>;
> +        iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>,
> +            <&vpp_iommu M4U_PORT_L16A_CQI_R1>,
> +            <&vpp_iommu M4U_PORT_L16A_CQI_R2>,
> +            <&vpp_iommu M4U_PORT_L16A_BPCI_R1>,
> +            <&vpp_iommu M4U_PORT_L16A_LSCI_R1>,
> +            <&vpp_iommu M4U_PORT_L16A_RAWI_R2>,
> +            <&vpp_iommu M4U_PORT_L16A_RAWI_R3>,
> +            <&vpp_iommu M4U_PORT_L16A_UFDI_R2>,
> +            <&vpp_iommu M4U_PORT_L16A_UFDI_R3>,
> +            <&vpp_iommu M4U_PORT_L16A_RAWI_R4>,
> +            <&vpp_iommu M4U_PORT_L16A_RAWI_R5>,
> +            <&vpp_iommu M4U_PORT_L16A_AAI_R1>,
> +            <&vpp_iommu M4U_PORT_L16A_UFDI_R5>,
> +            <&vpp_iommu M4U_PORT_L16A_FHO_R1>,
> +            <&vpp_iommu M4U_PORT_L16A_AAO_R1>,
> +            <&vpp_iommu M4U_PORT_L16A_TSFSO_R1>,
> +            <&vpp_iommu M4U_PORT_L16A_FLKO_R1>;
> +      };
> +    };
> +