[PATCH v2] PCI: mediatek-gen3: Avoid PCIe resetting via PCIE_RSTB for Airoha EN7581 SoC

[Jianjun Wang (王建军)]

Hi Bjorn,

On Tue, 2024-11-05 at 14:57 -0600, Bjorn Helgaas wrote:
> External email : Please do not click links or open attachments until
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> 
> On Tue, Nov 05, 2024 at 07:13:52PM +0100, Lorenzo Bianconi wrote:
> > > On Mon, Nov 04, 2024 at 11:00:05PM +0100, Lorenzo Bianconi wrote:
> > > > Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB
> > > > signal
> > > > causing occasional PCIe link down issues. In order to overcome
> > > > the
> > > > problem, PCIE_RSTB signals are not asserted/released during
> > > > device probe or
> > > > suspend/resume phase and the PCIe block is reset using
> > > > REG_PCI_CONTROL
> > > > (0x88) and REG_RESET_CONTROL (0x834) registers available via
> > > > the clock
> > > > module.
> > > > Introduce flags field in the mtk_gen3_pcie_pdata struct in
> > > > order to
> > > > specify per-SoC capabilities.
> > > 
> > > Where does this alternate way of doing reset (using
> > > REG_PCI_CONTROL
> > > and REG_RESET_CONTROL) happen?  Why isn't there something in this
> > > patch to use that alternate method at the same points where
> > > PCIE_PE_RSTB is used?
> > 
> > REG_RESET_CONTROL (0x834) is already asserted/released in the
> > following flow:
> > 
> > mtk_pcie_en7581_power_up() -> reset_control_bulk_deassert() ->
> > en7523_reset_update()
> > 
https://urldefense.com/v3/__https://github.com/torvalds/linux/blob/master/drivers/clk/clk-en7523.c*L470__;Iw!!CTRNKA9wMg0ARbw!mB58-w-wCBlwng2b0U_dcXijrb0y9Z9T5Xb0uNqMeNLcNZkN4SkyGK8cXfcW0bSE5RX3wEfvYITZ3CFhgTZ_$
> > 
> > REG_PCI_CONTROL (0x88) is already asserted/released in the
> > following flow:
> > mtk_pcie_en7581_power_up() -> clk_bulk_enable() ->
> > en7581_pci_enable()
> > 
https://urldefense.com/v3/__https://github.com/torvalds/linux/blob/master/drivers/clk/clk-en7523.c*L385__;Iw!!CTRNKA9wMg0ARbw!mB58-w-wCBlwng2b0U_dcXijrb0y9Z9T5Xb0uNqMeNLcNZkN4SkyGK8cXfcW0bSE5RX3wEfvYITZ3L8Llrnw$
> 
> So IIUC, you're saying that on EN7581, the PCI hierarchy is reset by
> the soc->power_up() callback, mtk_pcie_en7581_power_up(), via
> REG_PCI_CONTROL and REG_RESET_CONTROL.
> 
> I assume the hierarchy is also reset by the non-EN7581 .power_up()
> callback, mtk_pcie_power_up()?
> 
> And prior to this patch, we reset the hierarchy *again* in
> mtk_pcie_startup_port() via PCIE_RST_CTRL_REG, but this causes
> occasional "link down" issues because of a EN7581 hardware defect.
> 
> So for EN7581, this patch skips the PCIE_RST_CTRL_REG reset in
> mtk_pcie_startup_port().
> 
> .power_up() and mtk_pcie_startup_port() are used both at probe time
> and in mtk_pcie_resume_noirq().  So after this patch, I assume:
> 
>   - EN7581 resets the hierarchy once at probe and resume instead of
>     twice.
> 
>   - Non-EN7581 resets the hierarchy twice at probe and resume.
> 
> I assume I'm missing something (maybe mtk_pcie_power_up() doesn't
> actually reset the hierarchy?) because I don't see why we would reset
> the hierarchy twice for either controller.

Non-EN7581 only reset once, the original intention of
mtk_pcie_power_up() is to perform some power-up things:
1. Release hardware resets(this is not PERST#, but the hardware IP's
reset).
2. Initialize the PHY through PHY APIs.
3. Power on and enable the MAC's clocks.

After these steps, we initialize the PCIe interface in
mtk_pcie_startup_port() and toggle PERST# to reset the hierarchy as
required by the PCIe Spec. At this point, the PCIe link should be
ready.

Thanks.

> 
> Bjorn
>