[PATCH net-next v5 5/5] net: phy: add driver for built-in 2.5G ethernet PHY on MT7988

[kernel test robot]

Hi Sky,

kernel test robot noticed the following build warnings:

[auto build test WARNING on net-next/main]

url:    https://github.com/intel-lab-lkp/linux/commits/Sky-Huang/net-phy-mediatek-Re-organize-MediaTek-ethernet-phy-drivers/20240530-115522
base:   net-next/main
patch link:    https://lore.kernel.org/r/20240530034844.11176-6-SkyLake.Huang%40mediatek.com
patch subject: [PATCH net-next v5 5/5] net: phy: add driver for built-in 2.5G ethernet PHY on MT7988
config: openrisc-randconfig-r121-20240531 (https://download.01.org/0day-ci/archive/20240531/202405310819.c3Dv1OM3-lkp@intel.com/config)
compiler: or1k-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240531/202405310819.c3Dv1OM3-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405310819.c3Dv1OM3-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/net/phy/mediatek/mtk-2p5ge.c:106:9: sparse: sparse: cast to restricted __be16

vim +106 drivers/net/phy/mediatek/mtk-2p5ge.c

    56	
    57	static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev)
    58	{
    59		struct mtk_i2p5ge_phy_priv *priv = phydev->priv;
    60		void __iomem *md32_en_cfg_base, *pmb_addr;
    61		struct device *dev = &phydev->mdio.dev;
    62		const struct firmware *fw;
    63		int ret, i;
    64		u16 reg;
    65	
    66		if (priv->fw_loaded)
    67			return 0;
    68	
    69		pmb_addr = ioremap(MT7988_2P5GE_PMB_BASE, MT7988_2P5GE_PMB_LEN);
    70		if (!pmb_addr)
    71			return -ENOMEM;
    72		md32_en_cfg_base = ioremap(MT7988_2P5GE_MD32_EN_CFG_BASE, MT7988_2P5GE_MD32_EN_CFG_LEN);
    73		if (!md32_en_cfg_base) {
    74			ret = -ENOMEM;
    75			goto free_pmb;
    76		}
    77	
    78		ret = request_firmware(&fw, MT7988_2P5GE_PMB, dev);
    79		if (ret) {
    80			dev_err(dev, "failed to load firmware: %s, ret: %d\n",
    81				MT7988_2P5GE_PMB, ret);
    82			goto free;
    83		}
    84	
    85		if (fw->size != MT7988_2P5GE_PMB_SIZE) {
    86			dev_err(dev, "Firmware size 0x%zx != 0x%x\n",
    87				fw->size, MT7988_2P5GE_PMB_SIZE);
    88			ret = -EINVAL;
    89			goto free;
    90		}
    91	
    92		reg = readw(md32_en_cfg_base);
    93		if (reg & MD32_EN) {
    94			phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
    95			usleep_range(10000, 11000);
    96		}
    97		phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
    98	
    99		/* Write magic number to safely stall MCU */
   100		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100);
   101		phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df);
   102	
   103		for (i = 0; i < MT7988_2P5GE_PMB_SIZE - 1; i += 4)
   104			writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
   105		release_firmware(fw);
 > 106		dev_info(dev, "Firmware date code: %x/%x/%x, version: %x.%x\n",
   107			 be16_to_cpu(*((uint16_t *)(fw->data + MT7988_2P5GE_PMB_SIZE - 8))),
   108			 *(fw->data + MT7988_2P5GE_PMB_SIZE - 6),
   109			 *(fw->data + MT7988_2P5GE_PMB_SIZE - 5),
   110			 *(fw->data + MT7988_2P5GE_PMB_SIZE - 2),
   111			 *(fw->data + MT7988_2P5GE_PMB_SIZE - 1));
   112	
   113		writew(reg & ~MD32_EN, md32_en_cfg_base);
   114		writew(reg | MD32_EN, md32_en_cfg_base);
   115		phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
   116		/* We need a delay here to stabilize initialization of MCU */
   117		usleep_range(7000, 8000);
   118		dev_info(dev, "Firmware loading/trigger ok.\n");
   119	
   120		priv->fw_loaded = true;
   121	
   122	free:
   123		iounmap(md32_en_cfg_base);
   124	free_pmb:
   125		iounmap(pmb_addr);
   126	
   127		return ret ? ret : 0;
   128	}
   129	

-- 
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