[PATCH net-next v6 5/5] net: phy: add driver for built-in 2.5G ethernet PHY on MT7988

[SkyLake Huang (黃啟澤)]

On Mon, 2024-06-03 at 20:40 +0100, Daniel Golle wrote:
>  	 
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>  On Mon, Jun 03, 2024 at 08:18:34PM +0800, Sky Huang wrote:
> > From: "SkyLake.Huang" <skylake.huang at mediatek.com>
> > +
> > +static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device
> *phydev,
> > +      phy_interface_t iface)
> > +{
> > +if (iface == PHY_INTERFACE_MODE_XGMII ||
> > +    iface == PHY_INTERFACE_MODE_INTERNAL)
> > +return RATE_MATCH_PAUSE;
> > +return RATE_MATCH_NONE;
> 
> As the phy is always connected in the same way internally inside the
> MT7988
> this check and destinction doesn't make sense to me.
> 
> Imho you should always return RATE_MATCH_PAUSE, unless the same PHY
> also
> exists in other SoCs and/or is connected in different interface
> modes.
> 
> In any way, please explain this part to us, especially in which
> situation
> exactly you want to return RATE_MATCH_NONE and for which reason.
> 
  Actually internal 2.5Gphy is planned to be conntected to both XFI-MAC 
and GMAC at very first: (2.5G speed relies on XGMII path and
1G/100M/10M rely on GMII/MII path)
+---------+       +--------+
|         |       |        |
| XFI-MAC |       |  GMAC  |
|         |       |        |
+---------+       +--------+
        |           |
        |           |
      (FCM)         |
    +-------+----------+
    | XGMII | GMII/MII |
    +------------------+
    |                  |
    |     built-in     |
    |      2.5Gphy     |
    |                  |
    +------------------+
  This phy's rate adaptation is implemented in FCM (flow control
module) on the XGMII path. So mt798x_2p5ge_phy_get_rate_matching() will
only return RATE_MATCH_PAUSE for this path.(for developing purpose)
  However, GMII/MII is deprecated later in our built-in 2.5Gphy
hardware design. So yes, you're right.
mt798x_2p5ge_phy_get_rate_matching() should always return
RATE_MATCH_PAUSE now. I'll change this in next version.

Sky