[PATCH v5 1/5] dt-bindings: media: add mediatek ISP3.0 sensor interface
Julien Stephan
jstephan at baylibre.com
Fri Jul 5 00:50:59 PDT 2024
Le jeu. 4 juil. 2024 à 18:27, Conor Dooley <conor at kernel.org> a écrit :
>
> On Thu, Jul 04, 2024 at 03:36:40PM +0200, Julien Stephan wrote:
> > From: Louis Kuo <louis.kuo at mediatek.com>
> >
> > This adds the bindings, for the mediatek ISP3.0 SENINF module embedded in
> > some Mediatek SoC, such as the mt8365
> >
> > Signed-off-by: Louis Kuo <louis.kuo at mediatek.com>
> > Signed-off-by: Phi-Bang Nguyen <pnguyen at baylibre.com>
> > Link: https://lore.kernel.org/r/20230807094940.329165-2-jstephan@baylibre.com
> > Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> > Reviewed-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> > Signed-off-by: Julien Stephan <jstephan at baylibre.com>
>
> I'm really confused by the link tag here. At first glance this looked
> like you were sending out something that had been applied by Laurent,
> given the Link, Rb and SoB from him. Why does he have a SoB on this
> patch? What did Phi-Bang Nguyen do with this patch, and should they have
> a Co-developed-by tag?
Hi Conor,
I was not using b4 for the previous revisions of this series, so maybe
I messed something up here :(
About Phi-Bang, this series has been in our internal tree for a long
time, and Phi-Bang has his SoB on it, so I kept it.
About Laurent's tags, they were already on v4. But maybe it was an
error ? Should I remove them?
>
> > ---
> > .../bindings/media/mediatek,mt8365-seninf.yaml | 275 +++++++++++++++++++++
> > MAINTAINERS | 7 +
> > 2 files changed, 282 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml
> > new file mode 100644
> > index 000000000000..aeabea9f956a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml
> > @@ -0,0 +1,275 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2023 MediaTek, BayLibre
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/media/mediatek,mt8365-seninf.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek Sensor Interface 3.0
> > +
> > +maintainers:
> > + - Laurent Pinchart <laurent.pinchart at ideasonboard.com>
> > + - Julien Stephan <jstephan at baylibre.com>
> > + - Andy Hsieh <andy.hsieh at mediatek.com>
> > +
> > +description:
> > + The ISP3.0 SENINF is the CSI-2 and parallel camera sensor interface found in
> > + multiple MediaTek SoCs. It can support up to three physical CSI-2 input ports,
> > + configured in DPHY (2 or 4 data lanes) or CPHY depending on the SoC.
> > + On the output side, SENINF can be connected either to CAMSV instance or
> > + to the internal ISP. CAMSV is used to bypass the internal ISP processing
> > + in order to connect either an external ISP, or a sensor (RAW, YUV).
> > +
> > +properties:
> > + compatible:
> > + const: mediatek,mt8365-seninf
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: Seninf camsys clock
> > + - description: Seninf top mux clock
> > +
> > + clock-names:
> > + items:
> > + - const: camsys
> > + - const: top_mux
> > +
> > + phys: true
> > +
> > + phy-names: true
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
> > + properties:
> > + port at 0:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
> > + unevaluatedProperties: false
> > + description: CSI0 or CSI0A port
> > +
> > + properties:
> > + endpoint:
> > + $ref: video-interfaces.yaml#
> > + unevaluatedProperties: false
> > +
> > + properties:
> > + clock-lanes:
> > + maxItems: 1
> > + data-lanes:
> > + minItems: 1
> > + maxItems: 4
> > +
> > + port at 1:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
> > + unevaluatedProperties: false
> > + description: CSI1 port
> > +
> > + properties:
> > + endpoint:
> > + $ref: video-interfaces.yaml#
> > + unevaluatedProperties: false
> > +
> > + properties:
> > + clock-lanes:
> > + maxItems: 1
> > + data-lanes:
> > + minItems: 1
> > + maxItems: 4
> > +
> > + port at 2:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
> > + unevaluatedProperties: false
> > + description: CSI2 port
> > +
> > + properties:
> > + endpoint:
> > + $ref: video-interfaces.yaml#
> > + unevaluatedProperties: false
> > +
> > + properties:
> > + clock-lanes:
> > + maxItems: 1
> > + data-lanes:
> > + minItems: 1
> > + maxItems: 4
> > +
> > + port at 3:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
> > + unevaluatedProperties: false
> > + description: CSI0B port
> > +
> > + properties:
> > + endpoint:
> > + $ref: video-interfaces.yaml#
> > + unevaluatedProperties: false
> > +
> > + properties:
> > + clock-lanes:
> > + maxItems: 1
> > + data-lanes:
> > + minItems: 1
> > + maxItems: 2
> > +
> > + port at 4:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: connection point for cam0
> > +
> > + port at 5:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: connection point for cam1
> > +
> > + port at 6:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: connection point for camsv0
> > +
> > + port at 7:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: connection point for camsv1
> > +
> > + port at 8:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: connection point for camsv2
> > +
> > + port at 9:
> > + $ref: /schemas/graph.yaml#/properties/port
> > + description: connection point for camsv3
> > +
> > + required:
> > + - port at 0
> > + - port at 1
> > + - port at 2
> > + - port at 3
> > + - port at 4
> > + - port at 5
> > + - port at 6
> > + - port at 7
> > + - port at 8
> > + - port at 9
> > +
> > +required:
> > + - compatible
> > + - interrupts
> > + - clocks
> > + - clock-names
> > + - power-domains
> > + - ports
> > +
> > +additionalProperties: false
> > +
> > +if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: mediatek,mt8365-seninf
>
> The binding supports only a single compatible, why is this complexity
> required? I don't see other devices being added in this series.
Right. The idea is that the number of PHYs depends on the SoC. In the
previous revision of the series,
the number of PHYs was not fixed, and Krzysztof asked me to fix it by
SoC. So I wanted to make it clear
that the number of PHYs depends on SoC but maybe I don't need that
complexity for that?
Is something like the following enough? And if complexity is added
later if some other SoC are added?
phys:
minItems: 2
maxItems: 2
description:
phandle to the PHYs connected to CSI0/A, CSI1, CSI0B
phy-names:
description:
list of PHYs names
minItems: 2
maxItems: 2
items:
type: string
enum:
- csi0
- csi1
- csi0b
uniqueItems: true
Cheers
Julien
>
> Cheers,
> Conor.
>
> > +then:
> > + properties:
> > + phys:
> > + minItems: 2
> > + maxItems: 2
> > + description:
> > + phandle to the PHYs connected to CSI0/A, CSI1, CSI0B
> > +
> > + phy-names:
> > + description:
> > + list of PHYs names
> > + minItems: 2
> > + maxItems: 2
> > + items:
> > + type: string
> > + enum:
> > + - csi0
> > + - csi1
> > + - csi0b
> > + uniqueItems: true
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