[PATCH 1/4] dt-bindings: media: add mediatek ISP3.0 sensor interface
Julien Stephan
jstephan at baylibre.com
Wed Jun 28 07:52:52 PDT 2023
From: Louis Kuo <louis.kuo at mediatek.com>
This adds the bindings, for the mediatek ISP3.0 SENINF module embedded in
some Mediatek SoC, such as the mt8365
Signed-off-by: Louis Kuo <louis.kuo at mediatek.com>
Signed-off-by: Phi-Bang Nguyen <pnguyen at baylibre.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
Signed-off-by: Julien Stephan <jstephan at baylibre.com>
---
.../media/mediatek,mt8365-seninf.yaml | 299 ++++++++++++++++++
MAINTAINERS | 7 +
2 files changed, 306 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml
new file mode 100644
index 000000000000..a54f785bb252
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml
@@ -0,0 +1,299 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2023 MediaTek, BayLibre
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mt8365-seninf.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Sensor Interface 3.0
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart at ideasonboard.com>
+ - Julien Stephan <jstephan at baylibre.com>
+ - Andy Hsieh <andy.hsieh at mediatek.com>
+
+description:
+ The ISP3.0 SENINF is the CSI-2 and parallel camera sensor interface found in
+ multiple MediaTek SoCs. It can support up to three physical CSI-2
+ input ports, configured in DPHY (2 or 4 data lanes) or CPHY depending on the soc.
+ On the output side, SENINF can be connected either to CAMSV instance or
+ to the internal ISP. CAMSV is used to bypass the internal ISP processing
+ in order to connect either an external ISP, or a sensor (RAW, YUV).
+
+properties:
+ compatible:
+ const: mediatek,mt8365-seninf
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Seninf camsys clock
+ - description: Seninf top mux clock
+
+ clock-names:
+ items:
+ - const: cam_seninf
+ - const: top_mux_seninf
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port at 0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: CSI0 or CSI0A port
+
+ properties:
+ phys:
+ maxItems: 1
+ description: phandle to the PHY connected to CSI0/CSI0A
+
+ patternProperties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ port at 1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: CSI1 port
+
+ properties:
+ phys:
+ maxItems: 1
+ description: phandle to the PHY connected to CSI1
+
+ patternProperties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ port at 2:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: CSI2 port
+
+ properties:
+ phys:
+ maxItems: 1
+ description: phandle to the PHY connected to CSI2
+
+ patternProperties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ port at 3:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: CSI0B port
+
+ properties:
+ phys:
+ maxItems: 1
+ description: phandle to the PHY connected to CSI0B
+
+ patternProperties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+ data-lanes:
+ minItems: 1
+ maxItems: 2
+
+ port at 4:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: connection point for cam0
+
+ patternProperties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ port at 5:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: connection point for cam1
+
+ patternProperties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ port at 6:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: connection point for camsv0
+
+ patternProperties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ port at 7:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: connection point for camsv1
+
+ patternProperties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ port at 8:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: connection point for camsv2
+
+ patternProperties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ port at 9:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: connection point for camsv3
+
+ patternProperties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ required:
+ - port at 0
+ - port at 1
+ - port at 2
+ - port at 3
+ - port at 4
+ - port at 5
+ - port at 6
+ - port at 7
+ - port at 8
+ - port at 9
+
+required:
+ - compatible
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mediatek,mt8365-clk.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/power/mediatek,mt8365-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ seninf: seninf at 15040000 {
+ compatible = "mediatek,mt8365-seninf";
+ reg = <0 0x15040000 0 0x6000>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&camsys CLK_CAM_SENIF>,
+ <&topckgen CLK_TOP_SENIF_SEL>;
+ clock-names = "cam_seninf", "top_mux_seninf";
+
+ power-domains = <&spm MT8365_POWER_DOMAIN_CAM>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+ phys = <&mipi_csi0 PHY_TYPE_DPHY>;
+ seninf_in1: endpoint {
+ clock-lanes = <2>;
+ data-lanes = <1 3 0 4>;
+ remote-endpoint = <&isp1_out>;
+ };
+ };
+
+ port at 1 {
+ reg = <1>;
+ };
+
+ port at 2 {
+ reg = <2>;
+ };
+
+ port at 3 {
+ reg = <3>;
+ };
+
+ port at 4 {
+ reg = <4>;
+ seninf_camsv1_endpoint: endpoint {
+ remote-endpoint = <&camsv1_endpoint>;
+ };
+ };
+
+ port at 5 {
+ reg = <5>;
+ };
+
+ port at 6 {
+ reg = <6>;
+ };
+
+ port at 7 {
+ reg = <7>;
+ };
+
+ port at 8 {
+ reg = <8>;
+ };
+
+ port at 9 {
+ reg = <9>;
+ };
+
+ };
+ };
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index e505023ffda1..1248a915a72f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13256,6 +13256,13 @@ M: Sean Wang <sean.wang at mediatek.com>
S: Maintained
F: drivers/char/hw_random/mtk-rng.c
+MEDIATEK ISP3.0 DRIVER
+M: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
+M: Julien Stephan <jstephan at baylibre.com>
+M: Andy Hsieh <andy.hsieh at mediatek.com>
+S: Supported
+F: Documentation/devicetree/bindings/media/mediatek,mt8365-seninf.yaml
+
MEDIATEK SMI DRIVER
M: Yong Wu <yong.wu at mediatek.com>
L: linux-mediatek at lists.infradead.org (moderated for non-subscribers)
--
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