[PATCH 3/6] media: dt-bindings: mediatek,vcodec: Remove VDEC_SYS for mt8183

Nícolas F. R. A. Prado nfraprado at collabora.com
Mon Jun 5 09:20:27 PDT 2023


The binding expects the first register space to be VDEC_SYS. But on
mt8183, which uses the stateless decoders, this space is used only for
controlling clocks and resets, which are better described as separate
clock-controller and reset-controller nodes.

In fact, in mt8173's devicetree there are already such separate
clock-controller nodes, which cause duplicate addresses between the
vdecsys node and the vcodec node. But for this SoC, since the stateful
decoder code makes other uses of the VDEC_SYS register space, it's not
straightforward to remove it.

In order to avoid the same address conflict to happen on mt8183,
since the only current use of the VDEC_SYS register space in
the driver is to read the status of a clock that indicates the hardware
is active, remove the VDEC_SYS register space from the binding and
describe an extra clock that will be used to directly check the hardware
status.

Also add reg-names to be able to tell that this new register schema is
used, so the driver can keep backward compatibility.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado at collabora.com>
---

 .../media/mediatek,vcodec-decoder.yaml        | 29 +++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml
index 6447e6c86f29..36a53b2484d6 100644
--- a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml
@@ -21,17 +21,21 @@ properties:
       - mediatek,mt8183-vcodec-dec
 
   reg:
+    minItems: 11
     maxItems: 12
 
+  reg-names:
+    minItems: 11
+
   interrupts:
     maxItems: 1
 
   clocks:
-    minItems: 1
+    minItems: 2
     maxItems: 8
 
   clock-names:
-    minItems: 1
+    minItems: 2
     maxItems: 8
 
   assigned-clocks: true
@@ -84,6 +88,24 @@ allOf:
         clock-names:
           items:
             - const: vdec
+            - const: active
+
+        reg:
+          maxItems: 11
+
+        reg-names:
+          items:
+            - const: misc
+            - const: ld
+            - const: top
+            - const: cm
+            - const: ad
+            - const: av
+            - const: pp
+            - const: hwd
+            - const: hwq
+            - const: hwb
+            - const: hwg
 
   - if:
       properties:
@@ -108,6 +130,9 @@ allOf:
             - const: venc_lt_sel
             - const: vdec_bus_clk_src
 
+        reg:
+          minItems: 12
+
 additionalProperties: false
 
 examples:
-- 
2.40.1




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