[PATCH v3] mmc: mtk-sd: reduce CIT for better performance

[Wenbin Mei (梅文彬)]

On Mon, 2023-06-05 at 10:48 +0200, AngeloGioacchino Del Regno wrote:
>  	 
> External email : Please do not click links or open attachments until
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>  Il 05/06/23 08:01, Wenbin Mei ha scritto:
> > CQHCI_SSC1 indicates to CQE the polling period to use when using
> periodic
> > SEND_QUEUE_STATUS(CMD13) polling.
> > Since MSDC CQE uses msdc_hclk as ITCFVAL, so driver should use hclk
> > frequency to get the actual time.
> > The default value 0x1000 that corresponds to 150us for MediaTek
> SoCs, let's
> > decrease it to 0x40 that corresponds to 2.35us, which can improve
> the
> > performance of some eMMC devices.
> > 
> > Signed-off-by: Wenbin Mei <wenbin.mei at mediatek.com>
> 
> OK! That's almost good now. There's only one consideration here: if
> MediaTek
> SoCs *require* msdc_hclk to calculate the CIT time, this means that
> this clock
> is critical for CQHCI functionality.
> 
> If msdc_hclk is not present, CQHCI cannot work correctly... so you
> don't have
> to cover the case in which there's no msdc_hclk clock: if that's not
> present,
> either fail probing, or disable CQHCI.
That's right, i will remove the else case.

Begards,
Wenbin
> 
> > ---
> >   drivers/mmc/host/cqhci.h  |  1 +
> >   drivers/mmc/host/mtk-sd.c | 47
> +++++++++++++++++++++++++++++++++++++++
> >   2 files changed, 48 insertions(+)
> > 
> > diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
> > index ba9387ed90eb..292b89ebd978 100644
> > --- a/drivers/mmc/host/cqhci.h
> > +++ b/drivers/mmc/host/cqhci.h
> > @@ -23,6 +23,7 @@
> >   /* capabilities */
> >   #define CQHCI_CAP0x04
> >   #define CQHCI_CAP_CS0x10000000 /* Crypto Support */
> > +#define CQHCI_CAP_ITCFMUL(x)(((x) & GENMASK(15, 12)) >> 12)
> >   
> >   /* configuration */
> >   #define CQHCI_CFG0x08
> > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> > index edade0e54a0c..c221ef8a6992 100644
> > --- a/drivers/mmc/host/mtk-sd.c
> > +++ b/drivers/mmc/host/mtk-sd.c
> > @@ -473,6 +473,7 @@ struct msdc_host {
> >   struct msdc_tune_para def_tune_para; /* default tune setting */
> >   struct msdc_tune_para saved_tune_para; /* tune result of
> CMD21/CMD19 */
> >   struct cqhci_host *cq_host;
> > +u32 cq_ssc1_time;
> >   };
> >   
> >   static const struct mtk_mmc_compatible mt2701_compat = {
> > @@ -2450,9 +2451,50 @@ static void
> msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
> >   }
> >   }
> >   
> > +static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
> 
> static int msdc_cqe_cit_cal(....)
> 
> > +{
> > +struct mmc_host *mmc = mmc_from_priv(host);
> > +struct cqhci_host *cq_host = mmc->cqe_private;
> > +u8 itcfmul;
> > +u32 hclk_freq;
> 
> hclk_freq should be `unsigned long`, as that's what clk_get_rate()
> returns.
> 
> > +u64 value;
> > +
> > +/* Since MSDC CQE uses msdc_hclk as ITCFVAL, so driver should use
> hclk
> > + * frequency to get the actual time for CIT.
> > + */
> 
> /*
>  * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as
> ITCFVAL
>  * so we multiply/divide the HCLK frequency by ITCFMUL to calculate
> the
>  * Send Status Command Idle Timer (CIT) value.
>  */
> if (!host->h_clk)
> return -EINVAL;
> 
> hclk_freq = clk_get_rate(host->h_clk);
> itcfmul = CQHCI_CAP_ITFCMUL(cqhci_readl(cq_host, CQHCI_CAP));
> switch (itcfmul) {
> ....
> }
> 
> > +if (host->h_clk) {
> > +hclk_freq = clk_get_rate(host->h_clk);
> > +itcfmul = CQHCI_CAP_ITCFMUL(cqhci_readl(cq_host, CQHCI_CAP));
> > +switch (itcfmul) {
> > +case 0x0:
> > +do_div(hclk_freq, 1000);
> > +break;
> > +case 0x1:
> > +do_div(hclk_freq, 100);
> > +break;
> > +case 0x2:
> > +do_div(hclk_freq, 10);
> > +break;
> > +case 0x3:
> > +break;
> > +case 0x4:
> > +hclk_freq = hclk_freq * 10;
> > +break;
> > +default:
> > +host->cq_ssc1_time = 0x40;
> > +return;
> > +value = hclk_freq * timer_ns;
> > +do_div(value, 1000000000ULL);
> > +host->cq_ssc1_time = value;
> > +} else {
> > +host->cq_ssc1_time = 0x40;
> > +}
> > +}
> > +
> >   static void msdc_cqe_enable(struct mmc_host *mmc)
> >   {
> >   struct msdc_host *host = mmc_priv(mmc);
> > +struct cqhci_host *cq_host = mmc->cqe_private;
> >   
> >   /* enable cmdq irq */
> >   writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
> > @@ -2462,6 +2504,9 @@ static void msdc_cqe_enable(struct mmc_host
> *mmc)
> >   msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
> >   /* default read data timeout 1s */
> >   msdc_set_timeout(host, 1000000000ULL, 0);
> > +
> > +/* Set the send status command idle timer */
> > +cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
> >   }
> >   
> >   static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
> > @@ -2803,6 +2848,8 @@ static int msdc_drv_probe(struct
> platform_device *pdev)
> >   /* cqhci 16bit length */
> >   /* 0 size, means 65536 so we don't have to -1 here */
> >   mmc->max_seg_size = 64 * 1024;
> > +/* Reduce CIT to 0x40 that corresponds to 2.35us */
> > +msdc_cqe_cit_cal(host, 2350);
> 
> ret = msdc_cqe_cit_cal(...)
> if (ret)
> goto release;
> 
> ^^^^ either fail probe, or use the eMMC/SD without CQHCI support.
> 
> Regards,
> Angelo
> 
> >   }
> >   
> >   ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
>