[PATCH v2,1/2] mtd: spi-nor: giga: gd25lq64c: Disable quad mode according to bus width

[Michael Walle]

Hi,

>> like a fundamental problem and that commit 39d1e3340c73 ("mtd: 
>> spi-nor:
>> Fix clearing of QE bit on lock()/unlock()") is broken in that regard.
> 
> what's wrong with the mentioned commit?

         } else if (nor->params->quad_enable) {
                 /*
                  * If the Status Register 2 Read command (35h) is not
                  * supported, we should at least be sure we don't
                  * change the value of the SR2 Quad Enable bit.
                  *
                  * We can safely assume that when the Quad Enable method 
is
                  * set, the value of the QE bit is one, as a consequence 
of the
                  * nor->params->quad_enable() call.
                  *
                  * We can safely assume that the Quad Enable bit is 
present in
                  * the Status Register 2 at BIT(1). According to the 
JESD216
                  * revB standard, BFPT DWORDS[15], bits 22:20, the 
16-bit
                  * Write Status (01h) command is available just for the 
cases
                  * in which the QE bit is described in SR2 at BIT(1).
                  */
                 sr_cr[1] = SR2_QUAD_EN_BIT1;
         } else {
                 sr_cr[1] = 0;
         }

"We can safely assume that when the Quad Enable method..". We cannot, if 
we
don't have 4 I/O lines. The quad_enable is just the op how to do it, but 
not
*if* can do it. It seems to be missing the same check as the
spi_nor_quad_enable(). But I'm not sure if it's that simple.

-michael