[PATCH v2,1/2] mtd: spi-nor: giga: gd25lq64c: Disable quad mode according to bus width

[Hsin-Yi Wang]

On Wed, Aug 16, 2023 at 6:42 PM Hsin-Yi Wang <hsinyi at chromium.org> wrote:
>
> gd25lq64c has Quad Enable Requirement flag parsed as
> BFPT_DWORD15_QER_SR2_BIT1_BUGGY in BFPT, even if spi-{rx/tx}-bus-width
> set as non QUAD, eg. 0, 1, 2... Thus quad_enable will not be NULL and
> quad enable (QE) bit will be set to 1 by default. According to
> datasheet[1], if QE bit is enabled, WP pin will become IO pin and the
> system can't use write protection feature, and it's also not recommended
> to set QE bit to 1[1].
>
> Add a post_bfpt fixup that reads spi-rx-bus-width to remove quad_enable
> if the width is set to below QUAD mode.
>
> [1]
> https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-00012-GD25LQ64C-Rev3.4.pdf
> page 13
>
> Signed-off-by: Hsin-Yi Wang <hsinyi at chromium.org>
> ---
change log:
v1->v2: read bus width property in driver instead of creating a
duplicate dt property.
v1 link: https://lore.kernel.org/lkml/20230815154412.713846-1-hsinyi@chromium.org/
---
>  drivers/mtd/spi-nor/gigadevice.c | 28 +++++++++++++++++++++++++++-
>  1 file changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
> index d57ddaf1525b3..8ea89e1858f9b 100644
> --- a/drivers/mtd/spi-nor/gigadevice.c
> +++ b/drivers/mtd/spi-nor/gigadevice.c
> @@ -33,6 +33,31 @@ static const struct spi_nor_fixups gd25q256_fixups = {
>         .post_bfpt = gd25q256_post_bfpt,
>  };
>
> +static int
> +gd25lq64c_post_bfpt(struct spi_nor *nor,
> +                   const struct sfdp_parameter_header *bfpt_header,
> +                   const struct sfdp_bfpt *bfpt)
> +{
> +       struct device_node *np = spi_nor_get_flash_node(nor);
> +       u32 value;
> +
> +       /*
> +        * Even if spi-{tx,rx}-bus-width is set to DUAL mode, due to the QER
> +        * flag parsed from BFPT is BFPT_DWORD15_QER_SR2_BIT1_BUGGY, so the
> +        * quad_enable will be set and QE bit set to 1.
> +        */
> +       if (!of_property_read_u32(np, "spi-rx-bus-width", &value)) {
> +               if (value <= 2)
> +                       nor->params->quad_enable = NULL;
> +       }
> +
> +       return 0;
> +}
> +
> +static struct spi_nor_fixups gd25lq64c_fixups = {
> +       .post_bfpt = gd25lq64c_post_bfpt,
> +};
> +
>  static const struct flash_info gigadevice_nor_parts[] = {
>         { "gd25q16", INFO(0xc84015, 0, 64 * 1024,  32)
>                 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
> @@ -53,7 +78,8 @@ static const struct flash_info gigadevice_nor_parts[] = {
>         { "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128)
>                 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
> -                             SPI_NOR_QUAD_READ) },
> +                             SPI_NOR_QUAD_READ)
> +               .fixups = &gd25lq64c_fixups },
>         { "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256)
>                 FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>                 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
> --
> 2.41.0.694.ge786442a9b-goog
>