[PATCH 08/10] clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents

[AngeloGioacchino Del Regno]

Il 07/09/22 05:49, Chen-Yu Tsai ha scritto:
> Hi,
> 
> On Mon, Sep 5, 2022 at 6:04 PM AngeloGioacchino Del Regno
> <angelogioacchino.delregno at collabora.com> wrote:
>>
>> These PLLs are conflicting with GPU rates that can be generated by
>> the GPU-dedicated MFGPLL and would require a special clock handler
>> to be used, for very little and ignorable power consumption benefits.
>> Also, we're in any case unable to set the rate of these PLLs to
>> something else that is sensible for this task, so simply drop them:
>> this will make the GPU to be clocked exclusively from MFGPLL for
>> "fast" rates, while still achieving the right "safe" rate during
>> PLL frequency locking.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
>> ---
>>   drivers/clk/mediatek/clk-mt8195-topckgen.c | 2 --
>>   1 file changed, 2 deletions(-)
>>
>> diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c
>> index 4dde23bece66..6ff610c101ae 100644
>> --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c
>> +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c
>> @@ -301,8 +301,6 @@ static const char * const ipu_if_parents[] = {
>>   static const char * const mfg_parents[] = {
>>          "clk26m",
>>          "mainpll_d5_d2",
>> -       "univpll_d6",
>> -       "univpll_d7"
> 
> I'd just comment them out and leave a note about it. Or remove them but
> leave a note. Removed code will not be obvious to others. And given this
> is probably the only public documentation of the hardware, it'd be a shame
> to lose evidence of it.
> 

That's fair, I totally agree with you.
I'll send a v2 that adds a comment on top of mfg_parents explaining the
possible parents and why d6/d7 were left out.

Thanks,
Angelo