[RESEND v3 2/3] dt-bindings: reset: mt8188: add toprgu reset-controller header file

[Guenter Roeck]

On Wed, Oct 26, 2022 at 02:33:26PM +0800, Runyang Chen wrote:
> From: Runyang Chen <runyang.chen at mediatek.com>
> 
> Add toprgu reset-controller header file for MT8188
> 
> Signed-off-by: Runyang Chen <runyang.chen at mediatek.com>
> Acked-by: Rob Herring <robh at kernel.org>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>

Reviewed-by: Guenter Roeck <linux at roeck-us.net>

> ---
>  include/dt-bindings/reset/mt8188-resets.h | 36 +++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>  create mode 100644 include/dt-bindings/reset/mt8188-resets.h
> 
> diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h
> new file mode 100644
> index 000000000000..377cdfda82a9
> --- /dev/null
> +++ b/include/dt-bindings/reset/mt8188-resets.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + * Author: Runyang Chen <runyang.chen at mediatek.com>
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188
> +#define _DT_BINDINGS_RESET_CONTROLLER_MT8188
> +
> +#define MT8188_TOPRGU_CONN_MCU_SW_RST          0
> +#define MT8188_TOPRGU_INFRA_GRST_SW_RST        1
> +#define MT8188_TOPRGU_IPU0_SW_RST              2
> +#define MT8188_TOPRGU_IPU1_SW_RST              3
> +#define MT8188_TOPRGU_IPU2_SW_RST              4
> +#define MT8188_TOPRGU_AUD_ASRC_SW_RST          5
> +#define MT8188_TOPRGU_INFRA_SW_RST             6
> +#define MT8188_TOPRGU_MMSYS_SW_RST             7
> +#define MT8188_TOPRGU_MFG_SW_RST               8
> +#define MT8188_TOPRGU_VENC_SW_RST              9
> +#define MT8188_TOPRGU_VDEC_SW_RST              10
> +#define MT8188_TOPRGU_CAM_VCORE_SW_RST         11
> +#define MT8188_TOPRGU_SCP_SW_RST               12
> +#define MT8188_TOPRGU_APMIXEDSYS_SW_RST        13
> +#define MT8188_TOPRGU_AUDIO_SW_RST             14
> +#define MT8188_TOPRGU_CAMSYS_SW_RST            15
> +#define MT8188_TOPRGU_MJC_SW_RST               16
> +#define MT8188_TOPRGU_PERI_SW_RST              17
> +#define MT8188_TOPRGU_PERI_AO_SW_RST           18
> +#define MT8188_TOPRGU_PCIE_SW_RST              19
> +#define MT8188_TOPRGU_ADSPSYS_SW_RST           21
> +#define MT8188_TOPRGU_DPTX_SW_RST              22
> +#define MT8188_TOPRGU_SPMI_MST_SW_RST          23
> +
> +#define MT8188_TOPRGU_SW_RST_NUM               24
> +
> +#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */