[PATCH v2 3/7] dts: arm64: mt8195: add MMSYS and MUTEX configuration for VPPSYS

[Moudy Ho]

From: "Roy-CW.Yeh" <roy-cw.yeh at mediatek.com>

Compatible names, node names, and GCE client registers for
VPPSYS0 and VPPSYS1 should be renamed or added to match
the binding file requirements.
Also, add two nodes for MT8195 VPPSYS MUTEX.

Signed-off-by: Roy-CW.Yeh <roy-cw.yeh at mediatek.com>
Signed-off-by: Moudy Ho <moudy.ho at mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 30 ++++++++++++++++++++----
 1 file changed, 26 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..3e73bd58e54d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1476,12 +1476,23 @@
 			#clock-cells = <1>;
 		};
 
-		vppsys0: clock-controller at 14000000 {
-			compatible = "mediatek,mt8195-vppsys0";
+		vppsys0: syscon at 14000000 {
+			compatible = "mediatek,mt8195-vppsys0",
+				     "mediatek,mt8195-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		mutex at 1400f000 {
+			compatible = "mediatek,mt8195-vpp-mutex";
+			reg = <0 0x1400f000 0 0x1000>;
+			interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
+			clocks = <&vppsys0 CLK_VPP0_MUTEX>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+		};
+
 		smi_sub_common_vpp0_vpp1_2x1: smi at 14010000 {
 			compatible = "mediatek,mt8195-smi-sub-common";
 			reg = <0 0x14010000 0 0x1000>;
@@ -1581,12 +1592,23 @@
 			power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
 		};
 
-		vppsys1: clock-controller at 14f00000 {
-			compatible = "mediatek,mt8195-vppsys1";
+		vppsys1: syscon at 14f00000 {
+			compatible = "mediatek,mt8195-vppsys1",
+				     "mediatek,mt8195-mmsys", "syscon";
 			reg = <0 0x14f00000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		mutex at 14f01000 {
+			compatible = "mediatek,mt8195-vpp-mutex";
+			reg = <0 0x14f01000 0 0x1000>;
+			interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
+			clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+		};
+
 		larb5: larb at 14f02000 {
 			compatible = "mediatek,mt8195-smi-larb";
 			reg = <0 0x14f02000 0 0x1000>;
-- 
2.18.0