[v2, 0/2] Fix broken SET/CLR mode of a certain number of pins for MediaTek MT8385 SoC

[Balsam CHIHI]

On Mon, Nov 7, 2022 at 3:44 PM Linus Walleij <linus.walleij at linaro.org> wrote:
>
> On Fri, Oct 21, 2022 at 10:47 AM <bchihi at baylibre.com> wrote:
>
> > From: Balsam CHIHI <bchihi at baylibre.com>
> >
> > On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the modes correctly.
> > To fix this issue, we add a specific callback mt8365_set_clr_mode() for this specific SoC.
> > This callback uses the main R/W register to read/update/write the modes instead of using the SET/CLR register.
> >
> > This is the original patch series proposed by Fabien Parent <fparent at baylibre.com>.
> > "https://lore.kernel.org/linux-arm-kernel/20220530123425.689459-1-fparent@baylibre.com/"
> >
> > Changelog:
> > Changes in v2 :
> >         - Rebase on top of 6.1.0-rc1-next-20221020
> >         - Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
> >         - Add mt8365_set_clr_mode() callback
>
> Patches applied, no need to resend for small issues.
>
> Sorry for taking so long, I wanted some feedback from the Mediatek
> maintainers but haven't heard anything, so I just applied them.
>

Hi Linus,

I'm sorry for the delay.
Thank you very much.

Best regards,
Balsam.

> Yours,
> Linus Walleij