[PATCH v2 09/23] arm64: dts: Update cache properties for hisilicon

[Wei Xu]

Hi Pierre,

On 2022/11/7 23:57, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
> 
> Update the Device Trees accordingly.
> 
> Signed-off-by: Pierre Gondois <pierre.gondois at arm.com>

Applied to the HiSilicon arm64 dt tree.
Thanks!

Best Regards,
Wei

> ---
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi |  2 ++
>  arch/arm64/boot/dts/hisilicon/hi6220.dtsi |  2 ++
>  arch/arm64/boot/dts/hisilicon/hip05.dtsi  |  4 ++++
>  arch/arm64/boot/dts/hisilicon/hip06.dtsi  |  4 ++++
>  arch/arm64/boot/dts/hisilicon/hip07.dtsi  | 16 ++++++++++++++++
>  5 files changed, 28 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index 8343d0cedde3..a57f35eb5ef6 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -203,10 +203,12 @@ CLUSTER_SLEEP_1: cluster-sleep-1 {
>  
>  		A53_L2: l2-cache0 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		A73_L2: l2-cache1 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  	};
>  
> diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> index ae0a7cfeeb47..f6d3202b0d1a 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
> @@ -186,10 +186,12 @@ cpu7: cpu at 103 {
>  
>  		CLUSTER0_L2: l2-cache0 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		CLUSTER1_L2: l2-cache1 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  	};
>  
> diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
> index 7b2abd10d3d6..5b2b1bfd0d2a 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
> @@ -211,18 +211,22 @@ cpu15: cpu at 20303 {
>  
>  		cluster0_l2: l2-cache0 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster1_l2: l2-cache1 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster2_l2: l2-cache2 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster3_l2: l2-cache3 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  	};
>  
> diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> index 2f8b03b0d365..291c2ee38288 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
> @@ -211,18 +211,22 @@ cpu15: cpu at 10303 {
>  
>  		cluster0_l2: l2-cache0 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster1_l2: l2-cache1 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster2_l2: l2-cache2 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster3_l2: l2-cache3 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  	};
>  
> diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> index 1a16662f8867..b8746fb959b5 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> @@ -842,66 +842,82 @@ cpu63: cpu at 70303 {
>  
>  		cluster0_l2: l2-cache0 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster1_l2: l2-cache1 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster2_l2: l2-cache2 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster3_l2: l2-cache3 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster4_l2: l2-cache4 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster5_l2: l2-cache5 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster6_l2: l2-cache6 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster7_l2: l2-cache7 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster8_l2: l2-cache8 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster9_l2: l2-cache9 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster10_l2: l2-cache10 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster11_l2: l2-cache11 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster12_l2: l2-cache12 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster13_l2: l2-cache13 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster14_l2: l2-cache14 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  
>  		cluster15_l2: l2-cache15 {
>  			compatible = "cache";
> +			cache-level = <2>;
>  		};
>  	};
>  
>