[PATCH 1/2] arm64: dts: mediatek: adjust whitespace around '='
Krzysztof Kozlowski
krzysztof.kozlowski at linaro.org
Thu May 26 13:44:01 PDT 2022
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
---
Output compared with dtx_diff and fdtdump.
---
arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 2 +-
.../boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 8 ++++----
arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 ++++----
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 10 +++++-----
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 4 ++--
arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 12 ++++++------
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 12 ++++++------
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++----
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 8 ++++----
arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 8 ++++----
10 files changed, 40 insertions(+), 40 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
index 11aa135aa0f3..9b1af9c80130 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts
@@ -106,7 +106,7 @@ &cpu2 {
};
ð {
- phy-mode ="rgmii-rxid";
+ phy-mode = "rgmii-rxid";
phy-handle = <ðernet_phy0>;
mediatek,tx-delay-ps = <1530>;
snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
index 2b9bf8dd14ec..ada06d3de1c9 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
@@ -336,14 +336,14 @@ mux {
i2c1_pins: i2c1-pins {
mux {
function = "i2c";
- groups = "i2c1_0";
+ groups = "i2c1_0";
};
};
i2c2_pins: i2c2-pins {
mux {
function = "i2c";
- groups = "i2c2_0";
+ groups = "i2c2_0";
};
};
@@ -366,14 +366,14 @@ conf {
irrx_pins: irrx-pins {
mux {
function = "ir";
- groups = "ir_1_rx";
+ groups = "ir_1_rx";
};
};
irtx_pins: irtx-pins {
mux {
function = "ir";
- groups = "ir_1_tx";
+ groups = "ir_1_tx";
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
index 596c073d8b05..3ee392d805d8 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
@@ -298,14 +298,14 @@ mux {
i2c1_pins: i2c1-pins {
mux {
function = "i2c";
- groups = "i2c1_0";
+ groups = "i2c1_0";
};
};
i2c2_pins: i2c2-pins {
mux {
function = "i2c";
- groups = "i2c2_0";
+ groups = "i2c2_0";
};
};
@@ -328,14 +328,14 @@ conf {
irrx_pins: irrx-pins {
mux {
function = "ir";
- groups = "ir_1_rx";
+ groups = "ir_1_rx";
};
};
irtx_pins: irtx-pins {
mux {
function = "ir";
- groups = "ir_1_tx";
+ groups = "ir_1_tx";
};
};
diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index dbcee8b4d8d8..146e18b5b1f4 100644
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -118,8 +118,8 @@ clk25m: oscillator {
};
psci {
- compatible = "arm,psci-0.2";
- method = "smc";
+ compatible = "arm,psci-0.2";
+ method = "smc";
};
pmu {
@@ -616,9 +616,9 @@ audsys: clock-controller at 11220000 {
afe: audio-controller {
compatible = "mediatek,mt7622-audio";
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "afe", "asys";
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "afe", "asys";
clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
<&topckgen CLK_TOP_AUD1_SEL>,
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index d2636a0ed152..e3a407d03551 100644
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -57,8 +57,8 @@ cpu3: cpu at 3 {
};
psci {
- compatible = "arm,psci-0.2";
- method = "smc";
+ compatible = "arm,psci-0.2";
+ method = "smc";
};
reserved-memory {
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
index 9c75fbb31f98..0d8f9459e35d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
@@ -300,8 +300,8 @@ da9211_vcpu_reg: BUCKA {
regulator-name = "VBUCKA";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
- regulator-min-microamp = <2000000>;
- regulator-max-microamp = <4400000>;
+ regulator-min-microamp = <2000000>;
+ regulator-max-microamp = <4400000>;
regulator-ramp-delay = <10000>;
regulator-always-on;
regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC
@@ -312,8 +312,8 @@ da9211_vgpu_reg: BUCKB {
regulator-name = "VBUCKB";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
- regulator-min-microamp = <2000000>;
- regulator-max-microamp = <3000000>;
+ regulator-min-microamp = <2000000>;
+ regulator-max-microamp = <3000000>;
regulator-ramp-delay = <10000>;
};
};
@@ -374,8 +374,8 @@ &mmc0 {
mmc-hs400-1_8v;
cap-mmc-hw-reset;
hs400-ds-delay = <0x14015>;
- mediatek,hs200-cmd-int-delay=<30>;
- mediatek,hs400-cmd-int-delay=<14>;
+ mediatek,hs200-cmd-int-delay = <30>;
+ mediatek,hs400-cmd-int-delay = <14>;
mediatek,hs400-cmd-resp-sel-rising;
vmmc-supply = <&mt6397_vemc_3v3_reg>;
vqmmc-supply = <&mt6397_vio18_reg>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
index 4fa1e93302c7..0b5f154007be 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@@ -122,8 +122,8 @@ da9211_vcpu_reg: BUCKA {
regulator-name = "VBUCKA";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
- regulator-min-microamp = <2000000>;
- regulator-max-microamp = <4400000>;
+ regulator-min-microamp = <2000000>;
+ regulator-max-microamp = <4400000>;
regulator-ramp-delay = <10000>;
regulator-always-on;
};
@@ -132,8 +132,8 @@ da9211_vgpu_reg: BUCKB {
regulator-name = "VBUCKB";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1310000>;
- regulator-min-microamp = <2000000>;
- regulator-max-microamp = <3000000>;
+ regulator-min-microamp = <2000000>;
+ regulator-max-microamp = <3000000>;
regulator-ramp-delay = <10000>;
};
};
@@ -148,8 +148,8 @@ &mmc0 {
bus-width = <8>;
max-frequency = <50000000>;
cap-mmc-highspeed;
- mediatek,hs200-cmd-int-delay=<26>;
- mediatek,hs400-cmd-int-delay=<14>;
+ mediatek,hs200-cmd-int-delay = <26>;
+ mediatek,hs400-cmd-int-delay = <14>;
mediatek,hs400-cmd-resp-sel-rising;
vmmc-supply = <&mt6397_vemc_3v3_reg>;
vqmmc-supply = <&mt6397_vio18_reg>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 40d7b47fc52e..5e903ab5884c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -246,9 +246,9 @@ pmu_a72 {
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
method = "smc";
- cpu_suspend = <0x84000001>;
- cpu_off = <0x84000002>;
- cpu_on = <0x84000003>;
+ cpu_suspend = <0x84000001>;
+ cpu_off = <0x84000002>;
+ cpu_on = <0x84000003>;
};
clk26m: oscillator0 {
@@ -1505,7 +1505,7 @@ larb5: larb at 19001000 {
vcodec_enc_vp8: vcodec at 19002000 {
compatible = "mediatek,mt8173-vcodec-enc-vp8";
- reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
+ reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 01e650251928..42b208132a88 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -295,8 +295,8 @@ pmu-a73 {
};
psci {
- compatible = "arm,psci-1.0";
- method = "smc";
+ compatible = "arm,psci-1.0";
+ method = "smc";
};
clk26m: oscillator {
@@ -504,7 +504,7 @@ power-domain at MT8183_POWER_DOMAIN_CONN {
power-domain at MT8183_POWER_DOMAIN_MFG_ASYNC {
reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>;
- clocks = <&topckgen CLK_TOP_MUX_MFG>;
+ clocks = <&topckgen CLK_TOP_MUX_MFG>;
clock-names = "mfg";
#address-cells = <1>;
#size-cells = <0>;
@@ -1150,7 +1150,7 @@ i2c8: i2c at 1101b000 {
};
ssusb: usb at 11201000 {
- compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
+ compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
reg = <0 0x11201000 0 0x2e00>,
<0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
index db25a515e420..690dc7717f2c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
@@ -139,19 +139,19 @@ pins {
};
&u3phy0 {
- status="okay";
+ status = "okay";
};
&u3phy1 {
- status="okay";
+ status = "okay";
};
&u3phy2 {
- status="okay";
+ status = "okay";
};
&u3phy3 {
- status="okay";
+ status = "okay";
};
&uart0 {
--
2.34.1
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