[PATCH] clk: mediatek: Fix unused 'ops' field in mtk_pll_data

[Boris Lysov]

Hello, Angelo! 

On Wed, 18 May 2022 14:15:13 +0200
AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com> wrote:

> Il 15/05/22 14:24, Boris Lysov ha scritto:
> > From: Boris Lysov <arzamas-16 at mail.ee>
> > 
> > Allow to specify optional clk_ops in mtk_pll_data which will be picked up in
> > mtk_clk_register_pll. So far no already supported Mediatek SoC needs
> > non-default clk_ops for PLLs but instead of removing this field it will be
> > actually used in the future for supporting older SoCs (see [1] for details)
> > with quirky PLLs.
> > 
> 
> Hello Boris,
> 
> I disagree about this change and would rather see the ops pointer removed
> with fire.
> 
> I got that you're trying to do something about "quirky PLLs", but is it
> really about the PLLs that you're mentioning being "quirky", or are they
> simply a different IP?

To be honest I don't know exactly. mt6577 seems to share some common IP
patterns such as splitting the entire clock system into few smaller subsystems
such as apmixed (PLLs), topckgen (mux control), infra- and pericfg (internal
and peripheral gate control). On the other hand, mt6577 is quite an old SoC
(more on that in the end) and there are some differences about its operation
compared to modern SoCs and their drivers.

> Also, if it's just about a bit inversion and a bigger delay:
> 1. Bigger delay: Depending on how bigger, we may simply delay more by default
>     for all PLLs, even the ones that aren't requiring us to wait for longer...
>     ...after all, if it's about waiting for 10/20 *microseconds* more
> { snip }

According to the mt6577 datasheet the largest settling time is 10
*milli*seconds for AUDPLL [1]. In my opinion this is way too much to be set as
default for all mediatek devices.

> 2. Bit inversion: that can be solved simply with a flag in the
> prepare/unprepare ops for this driver... and if you want something that
> performs even better, sparing you a nanosecond or two, you can always assign
> an "inverted" callback for managing that single bit;

Not all mt6577 PLLs need bit inversion. 2 PLLs follow the common flow (set a
CON0_PWR_ON bit to start). 6 PLLs set this bit to 0 to start. And 1 PLL (which
is actually a DDS) needs to write a magic value to specific register (in
apmixed region) to start.
Is very unfortunate that I can't directly link the vomit-inducing downstream
code to prove the PLL situation due to its licensing but it's publicly
available on the internet [2] as a part of device manufacturers' obligations to
publish source code.

> 3. Different IP: mtk_clk_register_(name-of-the-new-ip)_pll() - I don't think
> that there's anything to explain to that one.
In my opinion this would introduce more duplicate code than just letting a
developer set custom clk_ops for a specific platform.

Huge thanks for your feedback!

P.S As I said above, mt6577 is old and in its current state [3] it's closer to
being a personal project than a serious mainlining attempt. I share and agree
with your opinion [4] on e-waste and is why I'm trying to put an effort into it.
What I don't have enough of is time and, sadly, expertise. Maybe it'd be better
for me to stay on github.

[1] MT6577 HSPA Smartphone Application Processor Datasheet v0.94, page 1200
[2] any linux v3.4 mt6577 kernel on github, see the 'enable_pll_op' function in
mediatek/platform/mt6577/kernel/core/mt6577_clock_manager.c 
[3] https://github.com/arzam16/linux-mt6577
[4] https://lists.infradead.org/pipermail/linux-mediatek/2022-May/041498.html

> Regards,
> Angelo
> 
> > This patch depends on series "clk: mediatek: Move to struct clk_hw provider
> > APIs" [2] by Chen-Yu Tsai.
> > 
> > [1]
> > https://lists.infradead.org/pipermail/linux-mediatek/2022-February/035093.html
> > [2]
> > https://lists.infradead.org/pipermail/linux-mediatek/2022-May/040921.html
> > 
> > Signed-off-by: Boris Lysov <arzamas-16 at mail.ee>
> > ---
> >   drivers/clk/mediatek/clk-pll.c | 5 ++++-
> >   1 file changed, 4 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> > index cabdf25a27f3..509959a325f0 100644
> > --- a/drivers/clk/mediatek/clk-pll.c
> > +++ b/drivers/clk/mediatek/clk-pll.c
> > @@ -347,7 +347,10 @@ static struct clk_hw *mtk_clk_register_pll(const
> > struct mtk_pll_data *data, 
> >   	init.name = data->name;
> >   	init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
> > -	init.ops = &mtk_pll_ops;
> > +	if (data->ops)
> > +		init.ops = data->ops;
> > +	else
> > +		init.ops = &mtk_pll_ops;
> >   	if (data->parent_name)
> >   		init.parent_names = &data->parent_name;
> >   	else
> > 
>