[PATCH v2] PCI: mediatek-gen3: Print LTSSM state when PCIe link down

[Jianjun Wang]

Hi Maintainers,

Gentle ping for this patch, if there is anything I can do to get this
patch merged, please let me know.

Thanks.

On Fri, 2022-04-22 at 14:33 +0800, Jianjun Wang wrote:
> Hi Maintainers,
> 
> Just gentle ping for this patch, if there is anything I can do to get
> this patch merged, please let me know.
> 
> Thanks.
> 
> On Tue, 2022-03-29 at 11:07 +0800, Jianjun Wang wrote:
> > Print current LTSSM state when PCIe link down instead of the
> > register
> > value, make it easier to get the link status.
> > 
> > Signed-off-by: Jianjun Wang <jianjun.wang at mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno at collabora.com>
> > ---
> > Changes in v2:
> > Print both of the register value and the LTSSM state.
> > ---
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 41
> > ++++++++++++++++++++-
> >  1 file changed, 40 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c
> > b/drivers/pci/controller/pcie-mediatek-gen3.c
> > index 6745076a02b9..c24e03c198b7 100644
> > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -153,6 +153,37 @@ struct mtk_gen3_pcie {
> >  	DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
> >  };
> >  
> > +/* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */
> > +static const char *const ltssm_str[] = {
> > +	"detect.quiet",			/* 0x00 */
> > +	"detect.active",		/* 0x01 */
> > +	"polling.active",		/* 0x02 */
> > +	"polling.compliance",		/* 0x03 */
> > +	"polling.configuration",	/* 0x04 */
> > +	"config.linkwidthstart",	/* 0x05 */
> > +	"config.linkwidthaccept",	/* 0x06 */
> > +	"config.lanenumwait",		/* 0x07 */
> > +	"config.lanenumaccept",		/* 0x08 */
> > +	"config.complete",		/* 0x09 */
> > +	"config.idle",			/* 0x0A */
> > +	"recovery.receiverlock",	/* 0x0B */
> > +	"recovery.equalization",	/* 0x0C */
> > +	"recovery.speed",		/* 0x0D */
> > +	"recovery.receiverconfig",	/* 0x0E */
> > +	"recovery.idle",		/* 0x0F */
> > +	"L0",				/* 0x10 */
> > +	"L0s",				/* 0x11 */
> > +	"L1.entry",			/* 0x12 */
> > +	"L1.idle",			/* 0x13 */
> > +	"L2.idle",			/* 0x14 */
> > +	"L2.transmitwake",		/* 0x15 */
> > +	"disable",			/* 0x16 */
> > +	"loopback.entry",		/* 0x17 */
> > +	"loopback.active",		/* 0x18 */
> > +	"loopback.exit",		/* 0x19 */
> > +	"hotreset",			/* 0x1A */
> > +};
> > +
> >  /**
> >   * mtk_pcie_config_tlp_header() - Configure a configuration TLP
> > header
> >   * @bus: PCI bus to query
> > @@ -327,8 +358,16 @@ static int mtk_pcie_startup_port(struct
> > mtk_gen3_pcie *pcie)
> >  				 !!(val & PCIE_PORT_LINKUP), 20,
> >  				 PCI_PM_D3COLD_WAIT * USEC_PER_MSEC);
> >  	if (err) {
> > +		const char *ltssm_state;
> > +		int ltssm_index;
> > +
> >  		val = readl_relaxed(pcie->base +
> > PCIE_LTSSM_STATUS_REG);
> > -		dev_err(pcie->dev, "PCIe link down, ltssm reg val:
> > %#x\n", val);
> > +		ltssm_index = PCIE_LTSSM_STATE(val);
> > +		ltssm_state = ltssm_index >= ARRAY_SIZE(ltssm_str) ?
> > +			      "Unknown state" : ltssm_str[ltssm_index];
> > +		dev_err(pcie->dev,
> > +			"PCIe link down, current ltssm state: %s
> > (%#x)\n",
> > +			ltssm_state, val);
> >  		return err;
> >  	}
> >  
> 
>