[PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes

[Matthias Brugger]

On 29/03/2022 11:09, allen-kh.cheng wrote:
> Hi Matthias,
> 
> On Fri, 2022-03-25 at 16:22 +0100, Matthias Brugger wrote:
>>
>> On 18/03/2022 15:45, Allen-KH Cheng wrote:
>>> Add vcodec lat and core nodes for mt8192 SoC.
>>>
>>> Signed-off-by: Allen-KH Cheng <allen-kh.cheng at mediatek.com>
>>> ---
>>>    arch/arm64/boot/dts/mediatek/mt8192.dtsi | 61
>>> ++++++++++++++++++++++++
>>>    1 file changed, 61 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> index 63893779b193..71ad3adeed51 100644
>>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>>> @@ -1285,6 +1285,67 @@
>>>    			power-domains = <&spm
>>> MT8192_POWER_DOMAIN_ISP2>;
>>>    		};
>>>    
>>> +		vcodec_dec: vcodec-dec at 16000000 {
>>> +			compatible = "mediatek,mt8192-vcodec-dec";
>>> +			reg = <0 0x16000000 0 0x1000>;	/* VDEC_SYS
>>> */
>>> +			mediatek,scp = <&scp>;
>>> +			iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
>>> +			#address-cells = <2>;
>>> +			#size-cells = <2>;
>>> +			ranges = <0 0 0 0x16000000 0 0x26000>;
>>> +
>>> +			vcodec_lat: vcodec-lat at 10000 {
>>> +				compatible = "mediatek,mtk-vcodec-lat";
>>> +				reg = <0x0 0x10000 0 0x800>;		
>>> /* VDEC_MISC */
>>> +				interrupts = <GIC_SPI 426
>>> IRQ_TYPE_LEVEL_HIGH 0>;
>>> +				iommus = <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
>>> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
>>> +					 <&vdecsys_soc
>>> CLK_VDEC_SOC_VDEC>,
>>> +					 <&vdecsys_soc
>>> CLK_VDEC_SOC_LAT>,
>>> +					 <&vdecsys_soc
>>> CLK_VDEC_SOC_LARB1>,
>>> +					 <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				clock-names = "vdec-sel", "vdec-soc-
>>> vdec", "vdec-soc-lat",
>>> +					      "vdec-vdec", "vdec-top";
>>
>> Clock names do not match binding description. We have superfluous
>> "vdec-"
>> prefix. Same holds for mtk-vcodec-core. Anway I applied that patch as
>> the driver
>> does not care about the clock name. In any case it would be good if
>> you could
>> send a follow-up patch to fix the clock name.
>>
>> Applied, thanks
>>
> 
> Sorry, This is our mistake. those clk names should not append "vdec-"
> prefix from Rob's suggestion [1]. ('vdec-' is redundant)
> 
> Please drop this patch in v5.18-next/dts64.  I will send the corrected
> version.
> 

Ok, I dropped the commit from the branch for now.

> I apologize any inconvenience caused.
> 

No worries.

Regards,
Matthias

> [1] https://lore.kernel.org/all/YYFCaHI%2FDASUz+Vu@robh.at.kernel.org/
> 
> Thanks,
> Allen
> 
>>> +				assigned-clocks = <&topckgen
>>> CLK_TOP_VDEC_SEL>;
>>> +				assigned-clock-parents = <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				power-domains = <&spm
>>> MT8192_POWER_DOMAIN_VDEC>;
>>> +			};
>>> +
>>> +			vcodec_core: vcodec-core at 25000 {
>>> +				compatible = "mediatek,mtk-vcodec-
>>> core";
>>> +				reg = <0 0x25000 0 0x1000>;	/*
>>> VDEC_CORE_MISC */
>>> +				interrupts = <GIC_SPI 425
>>> IRQ_TYPE_LEVEL_HIGH 0>;
>>> +				iommus = <&iommu0
>>> M4U_PORT_L4_VDEC_MC_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_UFO_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PP_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PRED_RD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PRED_WR_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_PPWRAP_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_TILE_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_VLD_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_VLD2_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_AVC_MV_EXT>,
>>> +					 <&iommu0
>>> M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
>>> +				clocks = <&topckgen CLK_TOP_VDEC_SEL>,
>>> +					 <&vdecsys CLK_VDEC_VDEC>,
>>> +					 <&vdecsys CLK_VDEC_LAT>,
>>> +					 <&vdecsys CLK_VDEC_LARB1>,
>>> +					 <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				clock-names = "vdec-sel", "vdec-soc-
>>> vdec", "vdec-soc-lat",
>>> +					      "vdec-vdec", "vdec-top";
>>> +				assigned-clocks = <&topckgen
>>> CLK_TOP_VDEC_SEL>;
>>> +				assigned-clock-parents = <&topckgen
>>> CLK_TOP_MAINPLL_D4>;
>>> +				power-domains = <&spm
>>> MT8192_POWER_DOMAIN_VDEC2>;
>>> +			};
>>> +		};
>>> +
>>>    		larb5: larb at 1600d000 {
>>>    			compatible = "mediatek,mt8192-smi-larb";
>>>    			reg = <0 0x1600d000 0 0x1000>;
>