[PATCH v1] soc: mediatek: pm-domains: Fix the power glitch issue

[Chen-Yu Tsai]

On Thu, Mar 10, 2022 at 9:20 AM Chun-Jie Chen
<chun-jie.chen at mediatek.com> wrote:
>
> Power reset maybe generate unexpected signal. In order to avoid
> the glitch issue, we need to enable isolation first to guarantee the
> stable signal when power reset is triggered.
>
> Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains")
> Signed-off-by: Chun-Jie Chen <chun-jie.chen at mediatek.com>

Reviewed-by: Chen-Yu Tsai <wenst at chromium.org>

> ---
> This patch is based on 5.17-rc1.
> ---
>  drivers/soc/mediatek/mtk-pm-domains.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
> index b762bc40f56b..0195f6c3396b 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> @@ -272,9 +272,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
>         clk_bulk_disable_unprepare(pd->num_subsys_clks, pd->subsys_clks);
>
>         /* subsys power off */
> -       regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
>         regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
>         regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);
> +       regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
>         regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);
>         regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);
>
> --
> 2.18.0
>
>
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