[PATCH v12 03/23] dt-bindings: mediatek: add ethdr definition for mt8195

[AngeloGioacchino Del Regno]

Il 07/03/22 03:33, Nancy.Lin ha scritto:
> Hi Angelo,
> 
> Thanks for the review.
> 
> On Wed, 2022-03-02 at 11:13 +0100, AngeloGioacchino Del Regno wrote:
>> Il 22/02/22 11:07, Nancy.Lin ha scritto:
>>> Add vdosys1 ETHDR definition.
>>>
>>> Signed-off-by: Nancy.Lin <nancy.lin at mediatek.com>
>>> Reviewed-by: Chun-Kuang Hu <chunkuang.hu at kernel.org>
>>> ---
>>>    .../display/mediatek/mediatek,ethdr.yaml      | 147
>>> ++++++++++++++++++
>>>    1 file changed, 147 insertions(+)
>>>    create mode 100644
>>> Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y
>>> aml
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr
>>> .yaml
>>> b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr
>>> .yaml
>>> new file mode 100644
>>> index 000000000000..131eed5eeeb7
>>> --- /dev/null
>>> +++
>>> b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr
>>> .yaml
>>> @@ -0,0 +1,147 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id:
>>> https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml*__;Iw!!CTRNKA9wMg0ARbw!y6qWSq3epOM61tyVt6ijw6CRNaNmcK382oF8TQ-a57UAcXvx8o1yIPd7pTKakQkU$
>>>   
>>> +$schema:
>>> https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!y6qWSq3epOM61tyVt6ijw6CRNaNmcK382oF8TQ-a57UAcXvx8o1yIPd7pTQVqP2v$
>>>   
>>> +
>>> +title: Mediatek Ethdr Device Tree Bindings
>>> +
>>> +maintainers:
>>> +  - Chun-Kuang Hu <chunkuang.hu at kernel.org>
>>> +  - Philipp Zabel <p.zabel at pengutronix.de>
>>> +
>>> +description: |
>>> +  ETHDR is designed for HDR video and graphics conversion in the
>>> external display path.
>>> +  It handles multiple HDR input types and performs tone mapping,
>>> color space/color
>>> +  format conversion, and then combine different layers, output the
>>> required HDR or
>>> +  SDR signal to the subsequent display path. This engine is
>>> composed of two video
>>> +  frontends, two graphic frontends, one video backend and a mixer.
>>> ETHDR has two
>>> +  DMA function blocks, DS and ADL. These two function blocks read
>>> the pre-programmed
>>> +  registers from DRAM and set them to HW in the v-blanking period.
>>> +
>>> +properties:
>>> +  compatible:
>>> +    items:
>>> +      - const: mediatek,mt8195-disp-ethdr
>>> +  reg:
>>> +    maxItems: 7
>>> +  reg-names:
>>> +    items:
>>> +      - const: mixer
>>> +      - const: vdo_fe0
>>> +      - const: vdo_fe1
>>> +      - const: gfx_fe0
>>> +      - const: gfx_fe1
>>> +      - const: vdo_be
>>> +      - const: adl_ds
>>> +  interrupts:
>>> +    minItems: 1
>>> +  iommus:
>>> +    description: The compatible property is DMA function blocks.
>>> +      Should point to the respective IOMMU block with master port
>>> as argument,
>>> +      see
>>> Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for
>>> +      details.
>>> +    minItems: 1
>>> +    maxItems: 2
>>> +  clocks:
>>> +    items:
>>> +      - description: mixer clock
>>> +      - description: video frontend 0 clock
>>> +      - description: video frontend 1 clock
>>> +      - description: graphic frontend 0 clock
>>> +      - description: graphic frontend 1 clock
>>> +      - description: video backend clock
>>> +      - description: autodownload and menuload clock
>>> +      - description: video frontend 0 async clock
>>> +      - description: video frontend 1 async clock
>>> +      - description: graphic frontend 0 async clock
>>> +      - description: graphic frontend 1 async clock
>>> +      - description: video backend async clock
>>> +      - description: ethdr top clock
>>> +  clock-names:
>>> +    items:
>>> +      - const: mixer
>>> +      - const: vdo_fe0
>>> +      - const: vdo_fe1
>>> +      - const: gfx_fe0
>>> +      - const: gfx_fe1
>>> +      - const: vdo_be
>>> +      - const: adl_ds
>>> +      - const: vdo_fe0_async
>>> +      - const: vdo_fe1_async
>>> +      - const: gfx_fe0_async
>>> +      - const: gfx_fe1_async
>>> +      - const: vdo_be_async
>>> +      - const: ethdr_top
>>> +  power-domains:
>>> +    maxItems: 1
>>> +  resets:
>>> +    maxItems: 5
>>> +  mediatek,gce-client-reg:
>>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>>> +    description: The register of display function block to be set
>>> by gce.
>>> +      There are 4 arguments in this property, gce node, subsys id,
>>> offset and
>>> +      register size. The subsys id is defined in the gce header of
>>> each chips
>>> +      include/include/dt-bindings/gce/<chip>-gce.h, mapping to the
>>> register of
>>> +      display function block.
>>> +
>>> +required:
>>> +  - compatible
>>> +  - reg
>>> +  - clocks
>>> +  - clock-names
>>> +  - interrupts
>>> +  - power-domains
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> +  - |
>>
>> Please fix inclusions and address/size cells.
>>
>> Thanks,
>> Angelo
>>
> 
> Because the patch has been applied to mediatek-drm-next [1].
> I saw that you have a patch for fixing this issue [2]. I think I will
> just remove this patch in the next revision. Do you think this is OK?
> 
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
> [2]
> https://patchwork.kernel.org/project/linux-mediatek/patch/20220304095458.12409-4-
> angelogioacchino.delregno at collabora.com/
> 
> Best,
> Nancy
> 

Yes, this is ok.

Thank you,
Angelo