[PATCH v2 4/6] arm64: dts: mt8192: Add display nodes

[Chen-Yu Tsai]

On Fri, Jul 1, 2022 at 5:06 PM Allen-KH Cheng
<allen-kh.cheng at mediatek.com> wrote:
>
> Add display nodes and gce info for mt8192 SoC.
>
> GCE (Global Command Engine) properties to the display nodes in order to
> enable the usage of the CMDQ (Command Queue), which is required for
> operating the display.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng at mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado at collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi | 137 +++++++++++++++++++++++
>  1 file changed, 137 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index a789b7c9b2af..c4dc8777f26c 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -6,6 +6,7 @@
>
>  /dts-v1/;
>  #include <dt-bindings/clock/mt8192-clk.h>
> +#include <dt-bindings/gce/mt8192-gce.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/memory/mt8192-larb-port.h>
> @@ -553,6 +554,15 @@
>                         assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
>                 };
>
> +               gce: mailbox at 10228000 {
> +                       compatible = "mediatek,mt8192-gce";
> +                       reg = <0 0x10228000 0 0x4000>;
> +                       interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       #mbox-cells = <2>;
> +                       clocks = <&infracfg CLK_INFRA_GCE>;
> +                       clock-names = "gce";
> +               };
> +
>                 scp_adsp: clock-controller at 10720000 {
>                         compatible = "mediatek,mt8192-scp_adsp";
>                         reg = <0 0x10720000 0 0x1000>;
> @@ -1186,9 +1196,22 @@
>                 mmsys: syscon at 14000000 {
>                         compatible = "mediatek,mt8192-mmsys", "syscon";
>                         reg = <0 0x14000000 0 0x1000>;
> +                       mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> +                                <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> +                       mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>                         #clock-cells = <1>;

This also needs #reset-cells = <1>; othewise

    resets = <&mmsys MT8192_MMSYS_SW0_RST_B_DISP_DSI0>;

in patch 5 will fail to be parsed by the kernel.

Can you add this in a separate patch?

>                 };
>

[...]

> +               ovl_2l2: ovl at 14014000 {
> +                       compatible = "mediatek,mt8192-disp-ovl-2l";
> +                       reg = <0 0x14014000 0 0x1000>;
> +                       interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +                       clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
> +                       iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
> +                                <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
> +                       mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> +               };
> +
> +               rdma4: rdma at 14015000 {
> +                       compatible = "mediatek,mt8192-disp-rdma";
> +                       reg = <0 0x14015000 0 0x1000>;
> +                       interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
> +                       clocks = <&mmsys CLK_MM_DISP_RDMA4>;
> +                       iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
> +                       mediatek,rdma-fifo-size = <2048>;
> +                       mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> +               };
> +

The aliases for these need to be added. Otherwise the display pipeline
will stall.


ChenYu