[PATCH v14 08/12] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0

[Jason-JH Lin]

Hi CK,

Thanks for the reviews.

On Tue, 2022-01-25 at 11:44 +0800, CK Hu wrote:
> Hi, Jason:
> 
> On Fri, 2022-01-07 at 18:14 +0800, jason-jh.lin wrote:
> > Add mt8195 vdosys0 clock driver name and routing table to
> > the driver data of mtk-mmsys.
> > 
> > Signed-off-by: jason-jh.lin <jason-jh.lin at mediatek.com>
> > Acked-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno at collabora.com>
> > ---
> > The vdosys1 impelmentation patch [1] will be dependened on this
> > patch.
> > [1] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
> > - 
> > 
https://patchwork.kernel.org/project/linux-mediatek/patch/20211208024426.15595-6-nancy.lin@mediatek.com/
> > ---
> >  drivers/soc/mediatek/mt8195-mmsys.h    | 220
> > +++++++++++++++++++++++++
> >  drivers/soc/mediatek/mtk-mmsys.c       |  11 ++
> >  include/linux/soc/mediatek/mtk-mmsys.h |   9 +
> >  3 files changed, 240 insertions(+)
> >  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> > 
> > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h
> > b/drivers/soc/mediatek/mt8195-mmsys.h
> > new file mode 100644
> > index 000000000000..e04cabdfa2dc
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> > @@ -0,0 +1,220 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +
> > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
> > +#define __SOC_MEDIATEK_MT8195_MMSYS_H
> > +
> > +#define MT8195_VDO0_OVL_MOUT_EN					
> > 0xf14
> > +/*
> > + * MT8195_VDO0_OVL_MOUT[2:0]: DISP_OVL0
> > + *   BIT(0) : DISP_RDMA0
> > + *   BIT(1) : DISP_WDMA0
> > + *   BIT(2): DISP_OVL1
> 
> I think these information is not necessary because we could get these
> information from mmsys_mt8195_routing_table[].
> 
> Regards,
> CK
> 
These comments was suggest by Fei at:

https://patchwork.kernel.org/project/linux-mediatek/patch/20210921155218.10387-10-jason-jh.lin@mediatek.com/#24546317

I've discussed with him that removing these information is fine.
So' I'll remove it at the next version.

> > + */
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			
> > BIT(0)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			
> > BIT(1)
> > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
> > +/*
> > + * MT8195_VDO0_OVL_MOUT[6:4]: DISP_OVL1
> > + *   BIT(0) : DISP_RDMA1
> > + *   BIT(1) : DISP_WDMA1
> > + *   BIT(2): DISP_OVL0
> > + */
> > 
> 
> [snip]
> 
> > +
> > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[]
> > =
> > {
> > +	{
> > +		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> > +		MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
> > +		MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
> > +	}, {
> > +		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
> > +		MT8195_VDO0_OVL_MOUT_EN,
> > MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
> > +		MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
> > +	}, {
> > +		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > +		MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT,

> Why this mask MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT is 0?

> > +		MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
> > +	}, {
> > +		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> > +		MT8195_VDO0_SEL_IN,

> Why this mask MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE is 0?

> > +		MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
> > +	}, {
> > +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > +		MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0,
> > +		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
> > +	}, {
> > +		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > +		MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT,

> Why this mask MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 is 0?

> Regards,
> CK

I'll fix the 0 mask problem with the define of GENMASK(h, l) for each
mux settings.

Regards,
Jason-JH.Lin

> > +		MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
> > +	}, {
> > +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > +		MT8195_VDO0_SEL_IN,
> > MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0,
> > +		MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
> > +	}, {
> > +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
> > +		MT8195_VDO0_SEL_OUT,
> > MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN,
> > +		MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
> > +	}, {
> > +		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> > +		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSI0,
> > +		MT8195_SOUT_DISP_DITHER0_TO_DSI0
> > +	}, {
> > +		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
> > +		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0,
> > +		MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
> > +	}, {
> > +		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
> > +		MT8195_VDO0_SEL_OUT,
> > MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE,
> > +		MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
> > +	}, {
> > +		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
> > +		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DP_INTF0,
> > +		MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
> > +	}
> > +};
> > +
> 
> 
-- 
Jason-JH Lin <jason-jh.lin at mediatek.com>