Looking for help with mt6577 clock driver

[Boris Lysov]

Hello!

I'm developing a mainline kernel for mt6577 which is a dual-core Cortex-A9
SoC for smartphones/tablets.

I'm stuck at the clock driver which looks hard to implement for such an old
platform using mainline codebase from Mediatek. I do see common patterns like
using various subsystems for clock management (apmixed, pericfg, mmsys) but
what I'm failing to understand is how are clocks related to each other (for
example muxed ones) and what exactly drives each clock. 

Analyzing Mediatek downstream kernel code [1][2] didn't help me much because it
works in a "write some magic values to fire everything up because why not?" [3]
way. Right now my approaches are dumping and analyzing hardware registers while
the device runs downstream kernel [4], and just a plain guesswork which I
think is rather unreliable. 

From §3.3 of [5] I understand that LKML is not a helpdesk but I still would
like to ask for any tips regarding writing a good clock driver, especially how
to determine how are clocks related to each other. Can someone from Mediatek
explain the PLL/clock/mux subsystem on mt6577 please?

Thanks.

[1] ALPS.JB.MP.V1.19_MBK77_TB_JB source code package (kernel v3.4.x)
[2] https://www.acer.com/ac/en/US/content/support-product/4817?b=1 in the
"Documents (2)" section. 
[3] mediatek/platform/mt6577/kernel/core/mt_clock_manager.c from [1] or [2]
[4]
https://github.com/arzam16/mt6577_kernel_Acer_B1_A71/commit/5a447eceda71723715af9cc215a67241efc83b3d
[5] http://vger.kernel.org/lkml/