[RESEND PATCH v3 2/2] clk: mediatek: clk-mt8195-vdo1: Reparent and set rate on vdo1_dpintf's parent

[Stephen Boyd]

Quoting Nícolas F. R. A. Prado (2022-08-16 12:32:56)
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> 
> Like it was done for the vdo0_dp_intf0_dp_intf clock (used for eDP),
> add the CLK_SET_RATE_PARENT flag to CLK_VDO1_DPINTF (used for DP)
> and also fix its parent clock name as it has to be "top_dp" for two
> reasons:
>  - This is its real parent!
>  - Likewise to eDP/VDO0 counterpart, we need clock source
>    selection on CLK_TOP_DP.
> 
> Fixes: 269987505ba9 ("clk: mediatek: Add MT8195 vdosys1 clock support")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Tested-by: Bo-Chen Chen <rex-bc.chen at mediatek.com>
> Reviewed-by: Bo-Chen Chen <rex-bc.chen at mediatek.com>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado at collabora.com>
> ---

Applied to clk-next