[RESEND PATCH v3 1/2] clk: mediatek: clk-mt8195-vdo0: Set rate on vdo0_dp_intf0_dp_intf's parent

[Stephen Boyd]

Quoting Nícolas F. R. A. Prado (2022-08-16 12:32:55)
> From: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> 
> Add the CLK_SET_RATE_PARENT flag to the CLK_VDO0_DP_INTF0_DP_INTF
> clock: this is required to trigger clock source selection on
> CLK_TOP_EDP, while avoiding to manage the enablement of the former
> separately from the latter in the displayport driver.
> 
> Fixes: 70282c90d4a2 ("clk: mediatek: Add MT8195 vdosys0 clock support")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> Tested-by: Bo-Chen Chen <rex-bc.chen at mediatek.com>
> Reviewed-by: Bo-Chen Chen <rex-bc.chen at mediatek.com>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado at collabora.com>
> 
> ---

Applied to clk-next