[PATCH v6 11/34] iommu/mediatek: Add a flag NON_STD_AXI
Matthias Brugger
matthias.bgg at gmail.com
Thu Apr 28 07:52:53 PDT 2022
On 07/04/2022 09:57, Yong Wu wrote:
> Add a new flag NON_STD_AXI, All the previous SoC support this flag.
> Prepare for adding infra and apu iommu which don't support this.
>
> Signed-off-by: Yong Wu <yong.wu at mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno at collabora.com>
> ---
> drivers/iommu/mtk_iommu.c | 16 ++++++++++------
> 1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 92f172a772d1..e7008a20ec74 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -122,6 +122,7 @@
> #define IOVA_34_EN BIT(8)
> #define SHARE_PGTABLE BIT(9) /* 2 HW share pgtable */
> #define DCM_DISABLE BIT(10)
> +#define NOT_STD_AXI_MODE BIT(11)
>
> #define MTK_IOMMU_HAS_FLAG(pdata, _x) \
> ((((pdata)->flags) & (_x)) == (_x))
> @@ -785,7 +786,8 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
> regval = 0;
> } else {
> regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
> - regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
> + if (MTK_IOMMU_HAS_FLAG(data->plat_data, NOT_STD_AXI_MODE))
> + regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
That means that for mt8195 infra we write back the very same value we read from
REG_MMU_MISC_CTRL. Is this necessary?
Maybe we can come up with a different flag called STD_AXI_MODE and use something
like
} else if (!MTK_IOMMU_HAS_FLAG(data->plat_data, \
STD_AXI_MODE)) {
Reason is that it makes more sense to add a flag for one specific iommu instead
of adding a flag to the common case (iommu is not following standard AXI protocol).
What do you think?
Regards,
Matthias
> if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
> regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
> }
> @@ -1058,7 +1060,8 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = {
>
> static const struct mtk_iommu_plat_data mt2712_data = {
> .m4u_plat = M4U_MT2712,
> - .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE,
> + .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE |
> + NOT_STD_AXI_MODE,
> .hw_list = &m4ulist,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> .iova_region = single_domain,
> @@ -1068,7 +1071,8 @@ static const struct mtk_iommu_plat_data mt2712_data = {
>
> static const struct mtk_iommu_plat_data mt6779_data = {
> .m4u_plat = M4U_MT6779,
> - .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN,
> + .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN |
> + NOT_STD_AXI_MODE,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> .iova_region = single_domain,
> .iova_region_nr = ARRAY_SIZE(single_domain),
> @@ -1077,7 +1081,7 @@ static const struct mtk_iommu_plat_data mt6779_data = {
>
> static const struct mtk_iommu_plat_data mt8167_data = {
> .m4u_plat = M4U_MT8167,
> - .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR,
> + .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | NOT_STD_AXI_MODE,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> .iova_region = single_domain,
> .iova_region_nr = ARRAY_SIZE(single_domain),
> @@ -1087,7 +1091,7 @@ static const struct mtk_iommu_plat_data mt8167_data = {
> static const struct mtk_iommu_plat_data mt8173_data = {
> .m4u_plat = M4U_MT8173,
> .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
> - HAS_LEGACY_IVRP_PADDR,
> + HAS_LEGACY_IVRP_PADDR | NOT_STD_AXI_MODE,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
> .iova_region = single_domain,
> .iova_region_nr = ARRAY_SIZE(single_domain),
> @@ -1106,7 +1110,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
> static const struct mtk_iommu_plat_data mt8192_data = {
> .m4u_plat = M4U_MT8192,
> .flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN |
> - WR_THROT_EN | IOVA_34_EN,
> + WR_THROT_EN | IOVA_34_EN | NOT_STD_AXI_MODE,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> .iova_region = mt8192_multi_dom,
> .iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
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