[PATCH 5/7] arm64: dts: mediatek: mt8195-demo: enable ethernet
Macpaul Lin
macpaul.lin at mediatek.com
Tue Apr 26 23:25:23 PDT 2022
On Tue, 2022-04-26 at 15:41 +0200, Fabien Parent wrote:
> Enable ethernet on the MT8195 demo board.
>
> Signed-off-by: Fabien Parent <fparent at baylibre.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 108
> +++++++++++++++++++
> 1 file changed, 108 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> index 08cab3b3943b..0b7985486e2a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> @@ -80,6 +80,30 @@ optee_reserved: optee at 43200000 {
> };
> };
>
> +ð {
> + phy-mode = "rgmii-rxid";
> + phy-handle = <ð_phy>;
> + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
> + snps,reset-delays-us = <0 10000 10000>;
> + mediatek,tx-delay-ps = <2030>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <ð_default_pins>;
> + pinctrl-1 = <ð_sleep_pins>;
> + status = "okay";
> +
> + mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + eth_phy: phy at 1 {
> + compatible = "ethernet-phy-id001c.c916";
> + #phy-cells = <0>;
> + reg = <0x1>;
> + };
> + };
> +};
> +
> &i2c6 {
> clock-frequency = <400000>;
> pinctrl-0 = <&i2c6_pins>;
> @@ -260,6 +284,90 @@ &mt6359_vsram_others_ldo_reg {
> };
>
> &pio {
> + eth_default_pins: eth-default-pins {
> + pins-cc {
> + pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
> + <PINMUX_GPIO88__FUNC_GBE_TXEN>,
> + <PINMUX_GPIO87__FUNC_GBE_RXDV>,
> + <PINMUX_GPIO86__FUNC_GBE_RXC>;
> + drive-strength = <MTK_DRIVE_8mA>;
> + };
> +
> + pins-mdio {
> + pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
> + <PINMUX_GPIO90__FUNC_GBE_MDIO>;
> + input-enable;
> + };
> +
> + pins-phy-reset {
> + pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
> + };
> +
> + pins-power {
> + pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
> + <PINMUX_GPIO92__FUNC_GPIO92>;
> + output-high;
> + };
> +
> + pins-rxd {
> + pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
> + <PINMUX_GPIO82__FUNC_GBE_RXD2>,
> + <PINMUX_GPIO83__FUNC_GBE_RXD1>,
> + <PINMUX_GPIO84__FUNC_GBE_RXD0>;
> + };
> +
> + pins-txd {
> + pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
> + <PINMUX_GPIO78__FUNC_GBE_TXD2>,
> + <PINMUX_GPIO79__FUNC_GBE_TXD1>,
> + <PINMUX_GPIO80__FUNC_GBE_TXD0>;
> + drive-strength = <MTK_DRIVE_8mA>;
> + };
> + };
> +
> + eth_sleep_pins: eth-sleep-pins {
> + pins-cc {
> + pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
> + <PINMUX_GPIO88__FUNC_GPIO88>,
> + <PINMUX_GPIO87__FUNC_GPIO87>,
> + <PINMUX_GPIO86__FUNC_GPIO86>;
> + };
> +
> + pins-mdio {
> + pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
> + <PINMUX_GPIO90__FUNC_GPIO90>;
> + input-disable;
> + bias-disable;
> + };
> +
> + pins-phy-reset {
> + pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
> + input-disable;
> + bias-disable;
> + };
> +
> + pins-power {
> + pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
> + <PINMUX_GPIO92__FUNC_GPIO92>;
> + input-disable;
> + bias-disable;
> + };
> +
> + pins-rxd {
> + pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
> + <PINMUX_GPIO82__FUNC_GPIO82>,
> + <PINMUX_GPIO83__FUNC_GPIO83>,
> + <PINMUX_GPIO84__FUNC_GPIO84>;
> + };
> +
> + pins-txd {
> + pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
> + <PINMUX_GPIO78__FUNC_GPIO78>,
> + <PINMUX_GPIO79__FUNC_GPIO79>,
> + <PINMUX_GPIO80__FUNC_GPIO80>;
> + };
> + };
> +
> gpio_keys_pins: gpio-keys-pins {
> pins {
> pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
Tested-by: Macpaul Lin <macpaul.lin at mediatek.com>
Regards,
Macpaul Lin
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