[PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile
allen-kh.cheng
allen-kh.cheng at mediatek.com
Tue Apr 26 04:12:35 PDT 2022
Hi Matthias,
On Tue, 2022-04-26 at 12:28 +0200, Matthias Brugger wrote:
> Hi Allen,
>
> On 30/03/2022 09:34, allen-kh.cheng wrote:
> > Hi Matthias,
> >
> > On Tue, 2022-03-29 at 16:56 +0200, Matthias Brugger wrote:
> > >
> > > On 11/03/2022 14:07, Allen-KH Cheng wrote:
> > > > From: Allen-KH Cheng <Allen-KH.Cheng at mediatek.com>
> > > >
> > > > Add basic chip support for Mediatek MT8186.
> > > >
> > >
> > > Thanks for your patch. I would love to wait a bit longer to see
> > > if we
> > > can get
> > > the clock driver accepted. This way we could get rid of all the
> > > dummy
> > > clocks
> > > defined in here.
> > >
> > > Please send a new version once the clock driver is accepeted by
> > > Stephen, or ping
> > > this series in a few month.
> > >
> > > Thanks,
> > > Matthias
> > >
> >
> > Sure, that's great.
> >
> > I will send a new version after the clock driver is accepted.
> >
>
> I've seen that the clock driver got accepted. Can you please send a
> new patch
> adding the correct clocks to the nodes?
>
> Thanks a lot.
> Matthias
>
Sure, I am going to prepare the PATCH.
I will send a new patch ASAP.
Thanks,
Allen
> > Thanks,
> > Allen
> >
> > > > Signed-off-by: Allen-KH Cheng <Allen-KH.Cheng at mediatek.com>
> > > > ---
> > > > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > > > arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++
> > > > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356
> > > > ++++++++++++++++++++
> > > > 3 files changed, 381 insertions(+)
> > > > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-
> > > > evb.dts
> > > > create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > > >
> > > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile
> > > > b/arch/arm64/boot/dts/mediatek/Makefile
> > > > index 8c1e18032f9f..d32fdcf9afc6 100644
> > > > --- a/arch/arm64/boot/dts/mediatek/Makefile
> > > > +++ b/arch/arm64/boot/dts/mediatek/Makefile
> > > > @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-
> > > > kodama-sku32.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
> > > > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
> > > > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > > > b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > > > new file mode 100644
> > > > index 000000000000..eb23d1f19f87
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts
> > > > @@ -0,0 +1,24 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > > +/*
> > > > + * Copyright (C) 2022 MediaTek Inc.
> > > > + */
> > > > +/dts-v1/;
> > > > +#include "mt8186.dtsi"
> > > > +
> > > > +/ {
> > > > + model = "MediaTek MT8186 evaluation board";
> > > > + compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
> > > > +
> > > > + aliases {
> > > > + serial0 = &uart0;
> > > > + };
> > > > +
> > > > + chosen {
> > > > + stdout-path = "serial0:921600n8";
> > > > + };
> > > > +
> > > > + memory {
> > > > + device_type = "memory";
> > > > + reg = <0 0x40000000 0 0x80000000>;
> > > > + };
> > > > +};
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > > > b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > > > new file mode 100644
> > > > index 000000000000..aa45c75b18c7
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> > > > @@ -0,0 +1,356 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > > > +/*
> > > > + * Copyright (C) 2022 MediaTek Inc.
> > > > + * Author: Allen-KH Cheng <allenn-kh.cheng at mediatek.com>
> > > > + */
> > > > +/dts-v1/;
> > > > +
> > > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > > +#include <dt-bindings/interrupt-controller/irq.h>
> > > > +#include <dt-bindings/phy/phy.h>
> > > > +
> > > > +/ {
> > > > + compatible = "mediatek,mt8186";
> > > > + interrupt-parent = <&gic>;
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > +
> > > > + clk13m: oscillator0 {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <13000000>;
> > > > + clock-output-names = "clk13m";
> > > > + };
> > > > +
> > > > + clk26m: oscillator1 {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <26000000>;
> > > > + clock-output-names = "clk26m";
> > > > + };
> > > > +
> > > > + clk32k: oscillator2 {
> > > > + compatible = "fixed-clock";
> > > > + #clock-cells = <0>;
> > > > + clock-frequency = <32000>;
> > > > + clock-output-names = "clk32k";
> > > > + };
> > > > +
> > > > + cpus {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > +
> > > > + cpu0: cpu at 000 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0000>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu1: cpu at 100 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0100>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu2: cpu at 200 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0200>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu3: cpu at 300 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0300>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu4: cpu at 400 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0400>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu5: cpu at 500 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a55",
> > > > "arm,armv8";
> > > > + reg = <0x0500>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2000000000>;
> > > > + cpu-idle-states = <&cpuoff_l
> > > > &clusteroff_l>;
> > > > + next-level-cache = <&l2_0>;
> > > > + };
> > > > +
> > > > + cpu6: cpu at 600 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a75",
> > > > "arm,armv8";
> > > > + reg = <0x0600>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2050000000>;
> > > > + cpu-idle-states = <&cpuoff_b
> > > > &clusteroff_b>;
> > > > + next-level-cache = <&l2_1>;
> > > > + };
> > > > +
> > > > + cpu7: cpu at 700 {
> > > > + device_type = "cpu";
> > > > + compatible = "arm,cortex-a75",
> > > > "arm,armv8";
> > > > + reg = <0x0700>;
> > > > + enable-method = "psci";
> > > > + clock-frequency = <2050000000>;
> > > > + cpu-idle-states = <&cpuoff_b
> > > > &clusteroff_b>;
> > > > + next-level-cache = <&l2_1>;
> > > > + };
> > > > +
> > > > + cpu-map {
> > > > + cluster0 {
> > > > + core0 {
> > > > + cpu = <&cpu0>;
> > > > + };
> > > > +
> > > > + core1 {
> > > > + cpu = <&cpu1>;
> > > > + };
> > > > +
> > > > + core2 {
> > > > + cpu = <&cpu2>;
> > > > + };
> > > > +
> > > > + core3 {
> > > > + cpu = <&cpu3>;
> > > > + };
> > > > +
> > > > + core4 {
> > > > + cpu = <&cpu4>;
> > > > + };
> > > > +
> > > > + core5 {
> > > > + cpu = <&cpu5>;
> > > > + };
> > > > + };
> > > > +
> > > > + cluster1 {
> > > > + core0 {
> > > > + cpu = <&cpu6>;
> > > > + };
> > > > +
> > > > + core1 {
> > > > + cpu = <&cpu7>;
> > > > + };
> > > > + };
> > > > + };
> > > > +
> > > > + idle-states {
> > > > + entry-method = "arm,psci";
> > > > +
> > > > + cpuoff_l: cpu-off-l {
> > > > + compatible = "arm,idle-state";
> > > > + arm,psci-suspend-param =
> > > > <0x00010001>;
> > > > + local-timer-stop;
> > > > + entry-latency-us = <50>;
> > > > + exit-latency-us = <100>;
> > > > + min-residency-us = <1600>;
> > > > + };
> > > > +
> > > > + cpuoff_b: cpu-off-b {
> > > > + compatible = "arm,idle-state";
> > > > + arm,psci-suspend-param =
> > > > <0x00010001>;
> > > > + local-timer-stop;
> > > > + entry-latency-us = <50>;
> > > > + exit-latency-us = <100>;
> > > > + min-residency-us = <1400>;
> > > > + };
> > > > +
> > > > + clusteroff_l: cluster-off-l {
> > > > + compatible = "arm,idle-state";
> > > > + arm,psci-suspend-param =
> > > > <0x01010001>;
> > > > + local-timer-stop;
> > > > + entry-latency-us = <100>;
> > > > + exit-latency-us = <250>;
> > > > + min-residency-us = <2100>;
> > > > + };
> > > > +
> > > > + clusteroff_b: cluster-off-b {
> > > > + compatible = "arm,idle-state";
> > > > + arm,psci-suspend-param =
> > > > <0x01010001>;
> > > > + local-timer-stop;
> > > > + entry-latency-us = <100>;
> > > > + exit-latency-us = <250>;
> > > > + min-residency-us = <1900>;
> > > > + };
> > > > + };
> > > > +
> > > > + l2_0: l2-cache0 {
> > > > + compatible = "cache";
> > > > + next-level-cache = <&l3_0>;
> > > > + };
> > > > +
> > > > + l2_1: l2-cache1 {
> > > > + compatible = "cache";
> > > > + next-level-cache = <&l3_0>;
> > > > + };
> > > > +
> > > > + l3_0: l3-cache {
> > > > + compatible = "cache";
> > > > + };
> > > > + };
> > > > +
> > > > + psci {
> > > > + compatible = "arm,psci-1.0";
> > > > + method = "smc";
> > > > + };
> > > > +
> > > > + timer: timer {
> > > > + compatible = "arm,armv8-timer";
> > > > + interrupt-parent = <&gic>;
> > > > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> > > > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> > > > + clock-frequency = <13000000>;
> > > > + };
> > > > +
> > > > + soc {
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + compatible = "simple-bus";
> > > > + ranges;
> > > > +
> > > > + gic: interrupt-controller at c000000 {
> > > > + compatible = "arm,gic-v3";
> > > > + #interrupt-cells = <3>;
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > > > + #redistributor-regions = <1>;
> > > > + interrupt-parent = <&gic>;
> > > > + interrupt-controller;
> > > > + reg = <0 0x0c000000 0 0x40000>, //
> > > > distributor
> > > > + <0 0x0c040000 0 0x200000>; //
> > > > redistributor
> > > > + interrupts = <GIC_PPI 9
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + };
> > > > +
> > > > + watchdog: watchdog at 10007000 {
> > > > + compatible = "mediatek,mt8186-wdt",
> > > > + "mediatek,mt6589-wdt";
> > > > + mediatek,disable-extrst;
> > > > + reg = <0 0x10007000 0 0x1000>;
> > > > + #reset-cells = <1>;
> > > > + };
> > > > +
> > > > + systimer: timer at 10017000 {
> > > > + compatible = "mediatek,mt8186-timer",
> > > > + "mediatek,mt6765-timer";
> > > > + reg = <0 0x10017000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 207
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk13m>;
> > > > + };
> > > > +
> > > > + uart0: serial at 11002000 {
> > > > + compatible = "mediatek,mt8186-uart",
> > > > + "mediatek,mt6577-uart";
> > > > + reg = <0 0x11002000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 112
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>;
> > > > + clock-names = "baud", "bus";
> > > > + };
> > > > +
> > > > + uart1: serial at 11003000 {
> > > > + compatible = "mediatek,mt8186-uart",
> > > > + "mediatek,mt6577-uart";
> > > > + reg = <0 0x11003000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 113
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>;
> > > > + clock-names = "baud", "bus";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + uart2: serial at 11018000 {
> > > > + compatible = "mediatek,mt8186-uart",
> > > > + "mediatek,mt6577-uart";
> > > > + reg = <0 0x11018000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 246
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>;
> > > > + clock-names = "baud", "bus";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + mmc0: mmc at 11230000 {
> > > > + compatible = "mediatek,mt8186-mmc",
> > > > + "mediatek,mt8183-mmc";
> > > > + reg = <0 0x11230000 0 0x1000>,
> > > > + <0 0x11cd0000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 100
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>,
> > > > <&clk26m>,
> > > > + <&clk26m>;
> > > > + clock-names = "source", "hclk",
> > > > "source_cg",
> > > > "ahb_clk";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + mmc1: mmc at 11240000 {
> > > > + compatible = "mediatek,mt8186-mmc",
> > > > + "mediatek,mt8183-mmc";
> > > > + reg = <0 0x11240000 0 0x1000>,
> > > > + <0 0x11c90000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 101
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + clocks = <&clk26m>, <&clk26m>,
> > > > <&clk26m>;
> > > > + clock-names = "source", "hclk",
> > > > "source_cg";
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + u3phy0: t-phy at 11c80000 {
> > > > + compatible = "mediatek,mt8186-tphy",
> > > > + "mediatek,generic-tphy-
> > > > v2";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + ranges = <0x0 0x0 0x11c80000 0x1000>;
> > > > +
> > > > + u2port1: usb2-phy1 at 0 {
> > > > + reg = <0x0 0x700>;
> > > > + clocks = <&clk26m>;
> > > > + clock-names = "ref";
> > > > + #phy-cells = <1>;
> > > > + };
> > > > +
> > > > + u3port1: usb3-phy1 at 700 {
> > > > + reg = <0x700 0x900>;
> > > > + clocks = <&clk26m>;
> > > > + clock-names = "ref";
> > > > + #phy-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > + u3phy1: t-phy at 11ca0000 {
> > > > + compatible = "mediatek,mt8186-tphy",
> > > > + "mediatek,generic-tphy-
> > > > v2";
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + ranges = <0x0 0x0 0x11ca0000 0x1000>;
> > > > +
> > > > + u2port0: usb-phy at 0 {
> > > > + reg = <0x0 0x700>;
> > > > + clocks = <&clk26m>;
> > > > + clock-names = "ref";
> > > > + #phy-cells = <1>;
> > > > + mediatek,discth = <0x8>;
> > > > + };
> > > > + };
> > > > + };
> > > > +};
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