[PATCH 1/2] ASoC: dt-bindings: mediatek: mt8192: complete clocks and clock-names

Matthias Brugger matthias.bgg at gmail.com
Fri Apr 22 07:14:27 PDT 2022



On 19/04/2022 04:55, Allen-KH Cheng wrote:
> From: Jiaxin Yu <jiaxin.yu at mediatek.com>
> 
> Complete all clocks and clock-names be used for mt8192 SoC into dt-bindings.
> 
> Signed-off-by: Jiaxin Yu <jiaxin.yu at mediatek.com>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng at mediatek.com>

You missed to add Mark to the list. This patch should go through his branch. I 
added him now to the thread.

Reviewed-by: Matthias Brugger <matthias.bgg at gmail.com>

Regards,
Matthias

> ---
>   .../bindings/sound/mt8192-afe-pcm.yaml        | 165 +++++++++++++++++-
>   1 file changed, 157 insertions(+), 8 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> index 7a25bc9b8060..1b6b22a5732e 100644
> --- a/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> +++ b/Documentation/devicetree/bindings/sound/mt8192-afe-pcm.yaml
> @@ -39,20 +39,67 @@ properties:
>       maxItems: 1
>   
>     clocks:
> -    items:
> -      - description: AFE clock
> -      - description: ADDA DAC clock
> -      - description: ADDA DAC pre-distortion clock
> -      - description: audio infra sys clock
> -      - description: audio infra 26M clock
> +    minItems: 56
> +    maxItems: 56
>   
>     clock-names:
>       items:
>         - const: aud_afe_clk
>         - const: aud_dac_clk
>         - const: aud_dac_predis_clk
> +      - const: aud_adc_clk
> +      - const: aud_adda6_adc_clk
> +      - const: aud_apll22m_clk
> +      - const: aud_apll24m_clk
> +      - const: aud_apll1_tuner_clk
> +      - const: aud_apll2_tuner_clk
> +      - const: aud_tdm_clk
> +      - const: aud_tml_clk
> +      - const: aud_nle
> +      - const: aud_dac_hires_clk
> +      - const: aud_adc_hires_clk
> +      - const: aud_adc_hires_tml
> +      - const: aud_adda6_adc_hires_clk
> +      - const: aud_3rd_dac_clk
> +      - const: aud_3rd_dac_predis_clk
> +      - const: aud_3rd_dac_tml
> +      - const: aud_3rd_dac_hires_clk
>         - const: aud_infra_clk
>         - const: aud_infra_26m_clk
> +      - const: top_mux_audio
> +      - const: top_mux_audio_int
> +      - const: top_mainpll_d4_d4
> +      - const: top_mux_aud_1
> +      - const: top_apll1_ck
> +      - const: top_mux_aud_2
> +      - const: top_apll2_ck
> +      - const: top_mux_aud_eng1
> +      - const: top_apll1_d4
> +      - const: top_mux_aud_eng2
> +      - const: top_apll2_d4
> +      - const: top_i2s0_m_sel
> +      - const: top_i2s1_m_sel
> +      - const: top_i2s2_m_sel
> +      - const: top_i2s3_m_sel
> +      - const: top_i2s4_m_sel
> +      - const: top_i2s5_m_sel
> +      - const: top_i2s6_m_sel
> +      - const: top_i2s7_m_sel
> +      - const: top_i2s8_m_sel
> +      - const: top_i2s9_m_sel
> +      - const: top_apll12_div0
> +      - const: top_apll12_div1
> +      - const: top_apll12_div2
> +      - const: top_apll12_div3
> +      - const: top_apll12_div4
> +      - const: top_apll12_divb
> +      - const: top_apll12_div5
> +      - const: top_apll12_div6
> +      - const: top_apll12_div7
> +      - const: top_apll12_div8
> +      - const: top_apll12_div9
> +      - const: top_mux_audio_h
> +      - const: top_clk26m_clk
>   
>   required:
>     - compatible
> @@ -88,13 +135,115 @@ examples:
>           clocks = <&audsys CLK_AUD_AFE>,
>                    <&audsys CLK_AUD_DAC>,
>                    <&audsys CLK_AUD_DAC_PREDIS>,
> +                 <&audsys CLK_AUD_ADC>,
> +                 <&audsys CLK_AUD_ADDA6_ADC>,
> +                 <&audsys CLK_AUD_22M>,
> +                 <&audsys CLK_AUD_24M>,
> +                 <&audsys CLK_AUD_APLL_TUNER>,
> +                 <&audsys CLK_AUD_APLL2_TUNER>,
> +                 <&audsys CLK_AUD_TDM>,
> +                 <&audsys CLK_AUD_TML>,
> +                 <&audsys CLK_AUD_NLE>,
> +                 <&audsys CLK_AUD_DAC_HIRES>,
> +                 <&audsys CLK_AUD_ADC_HIRES>,
> +                 <&audsys CLK_AUD_ADC_HIRES_TML>,
> +                 <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
> +                 <&audsys CLK_AUD_3RD_DAC>,
> +                 <&audsys CLK_AUD_3RD_DAC_PREDIS>,
> +                 <&audsys CLK_AUD_3RD_DAC_TML>,
> +                 <&audsys CLK_AUD_3RD_DAC_HIRES>,
>                    <&infracfg CLK_INFRA_AUDIO>,
> -                 <&infracfg CLK_INFRA_AUDIO_26M_B>;
> +                 <&infracfg CLK_INFRA_AUDIO_26M_B>,
> +                 <&topckgen CLK_TOP_AUDIO_SEL>,
> +                 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
> +                 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
> +                 <&topckgen CLK_TOP_AUD_1_SEL>,
> +                 <&topckgen CLK_TOP_APLL1>,
> +                 <&topckgen CLK_TOP_AUD_2_SEL>,
> +                 <&topckgen CLK_TOP_APLL2>,
> +                 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
> +                 <&topckgen CLK_TOP_APLL1_D4>,
> +                 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
> +                 <&topckgen CLK_TOP_APLL2_D4>,
> +                 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>,
> +                 <&topckgen CLK_TOP_APLL12_DIV0>,
> +                 <&topckgen CLK_TOP_APLL12_DIV1>,
> +                 <&topckgen CLK_TOP_APLL12_DIV2>,
> +                 <&topckgen CLK_TOP_APLL12_DIV3>,
> +                 <&topckgen CLK_TOP_APLL12_DIV4>,
> +                 <&topckgen CLK_TOP_APLL12_DIVB>,
> +                 <&topckgen CLK_TOP_APLL12_DIV5>,
> +                 <&topckgen CLK_TOP_APLL12_DIV6>,
> +                 <&topckgen CLK_TOP_APLL12_DIV7>,
> +                 <&topckgen CLK_TOP_APLL12_DIV8>,
> +                 <&topckgen CLK_TOP_APLL12_DIV9>,
> +                 <&topckgen CLK_TOP_AUDIO_H_SEL>,
> +                 <&clk26m>;
>           clock-names = "aud_afe_clk",
>                         "aud_dac_clk",
>                         "aud_dac_predis_clk",
> +                      "aud_adc_clk",
> +                      "aud_adda6_adc_clk",
> +                      "aud_apll22m_clk",
> +                      "aud_apll24m_clk",
> +                      "aud_apll1_tuner_clk",
> +                      "aud_apll2_tuner_clk",
> +                      "aud_tdm_clk",
> +                      "aud_tml_clk",
> +                      "aud_nle",
> +                      "aud_dac_hires_clk",
> +                      "aud_adc_hires_clk",
> +                      "aud_adc_hires_tml",
> +                      "aud_adda6_adc_hires_clk",
> +                      "aud_3rd_dac_clk",
> +                      "aud_3rd_dac_predis_clk",
> +                      "aud_3rd_dac_tml",
> +                      "aud_3rd_dac_hires_clk",
>                         "aud_infra_clk",
> -                      "aud_infra_26m_clk";
> +                      "aud_infra_26m_clk",
> +                      "top_mux_audio",
> +                      "top_mux_audio_int",
> +                      "top_mainpll_d4_d4",
> +                      "top_mux_aud_1",
> +                      "top_apll1_ck",
> +                      "top_mux_aud_2",
> +                      "top_apll2_ck",
> +                      "top_mux_aud_eng1",
> +                      "top_apll1_d4",
> +                      "top_mux_aud_eng2",
> +                      "top_apll2_d4",
> +                      "top_i2s0_m_sel",
> +                      "top_i2s1_m_sel",
> +                      "top_i2s2_m_sel",
> +                      "top_i2s3_m_sel",
> +                      "top_i2s4_m_sel",
> +                      "top_i2s5_m_sel",
> +                      "top_i2s6_m_sel",
> +                      "top_i2s7_m_sel",
> +                      "top_i2s8_m_sel",
> +                      "top_i2s9_m_sel",
> +                      "top_apll12_div0",
> +                      "top_apll12_div1",
> +                      "top_apll12_div2",
> +                      "top_apll12_div3",
> +                      "top_apll12_div4",
> +                      "top_apll12_divb",
> +                      "top_apll12_div5",
> +                      "top_apll12_div6",
> +                      "top_apll12_div7",
> +                      "top_apll12_div8",
> +                      "top_apll12_div9",
> +                      "top_mux_audio_h",
> +                      "top_clk26m_clk";
>       };
>   
>   ...



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