[PATCH 4/4] dt-bindings: media: mtk-vcodec: Add encoder power domain property

Matthias Brugger matthias.bgg at gmail.com
Fri Apr 22 06:47:27 PDT 2022



On 21/04/2022 05:51, Allen-KH Cheng wrote:
> From: Irui Wang <irui.wang at mediatek.com>
> 
> Add encoder power domain property
> 
> Signed-off-by: Irui Wang <irui.wang at mediatek.com>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng at mediatek.com>

Reviewed-by: Matthias Brugger <matthias.bgg at gmail.com>

> ---
>   .../devicetree/bindings/media/mediatek,vcodec-encoder.yaml | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
> index e7b65a91c92c..de2df6c6352c 100644
> --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
> +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
> @@ -41,6 +41,9 @@ properties:
>   
>     assigned-clock-parents: true
>   
> +  power-domains:
> +    maxItems: 1
> +
>     iommus:
>       minItems: 1
>       maxItems: 32
> @@ -74,6 +77,7 @@ required:
>     - iommus
>     - assigned-clocks
>     - assigned-clock-parents
> +  - power-domains
>   
>   allOf:
>     - if:
> @@ -135,6 +139,7 @@ examples:
>       #include <dt-bindings/clock/mt8173-clk.h>
>       #include <dt-bindings/memory/mt8173-larb-port.h>
>       #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/power/mt8173-power.h>
>   
>       vcodec_enc_avc: vcodec at 18002000 {
>         compatible = "mediatek,mt8173-vcodec-enc";
> @@ -156,6 +161,7 @@ examples:
>         clock-names = "venc_sel";
>         assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
>         assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
> +      power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
>       };
>   
>       vcodec_enc_vp8: vcodec at 19002000 {
> @@ -176,4 +182,5 @@ examples:
>         clock-names = "venc_lt_sel";
>         assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
>         assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
> +      power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
>       };



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