[PATCH v4,1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11
Rex-BC Chen
rex-bc.chen at mediatek.com
Tue Apr 12 00:37:48 PDT 2022
On Mon, 2022-04-11 at 10:31 +0800, xinlei.lee at mediatek.com wrote:
> From: Jitao Shi <jitao.shi at mediatek.com>
>
> Old sequence:
> 1. Pull the MIPI signal high
> 2. Delay & Dsi_reset
> 3. Set the dsi timing register
> 4. dsi clk & lanes leave ulp mode and enter hs mode
>
> The sequence after patching is:
> 1. Set the dsi timing register
> 2. Pull the MIPI signal high
> 3. Delay & Dsi_reset
> 4. dsi clk & lanes leave ulp mode and enter hs mode
>
> Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge
> API")
>
> Signed-off-by: Jitao Shi <jitao.shi at mediatek.com>
> Signed-off-by: Xinlei Lee <xinlei.lee at mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index ccb0511b9cd5..262c027d8c2f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
> mtk_dsi_reset_engine(dsi);
> mtk_dsi_phy_timconfig(dsi);
>
> - mtk_dsi_rxtx_control(dsi);
> - usleep_range(30, 100);
> - mtk_dsi_reset_dphy(dsi);
> mtk_dsi_ps_control_vact(dsi);
> mtk_dsi_set_vm_cmd(dsi);
> mtk_dsi_config_vdo_timing(dsi);
> mtk_dsi_set_interrupt_enable(dsi);
>
> + mtk_dsi_rxtx_control(dsi);
> + usleep_range(30, 100);
> + mtk_dsi_reset_dphy(dsi);
> mtk_dsi_clk_ulp_mode_leave(dsi);
> mtk_dsi_lane0_ulp_mode_leave(dsi);
> mtk_dsi_clk_hs_mode(dsi, 0);
Reviewed-by: Rex-BC Chen <rex-bc.chen at mediatek.com>
More information about the Linux-mediatek
mailing list