[PATCH v10 01/19] dt-bindings: ARM: Mediatek: Add new document bindings of MT8192 clock
Chun-Jie Chen
chun-jie.chen at mediatek.com
Mon Jun 28 06:01:45 PDT 2021
On Thu, 2021-06-24 at 14:59 -0600, Rob Herring wrote:
> On Wed, Jun 16, 2021 at 08:36:25AM +0800, Chun-Jie Chen wrote:
> > This patch adds the new binding documentation for system clock
> > and functional clock on Mediatek MT8192.
> >
> > Signed-off-by: Chun-Jie Chen <chun-jie.chen at mediatek.com>
> > ---
> > .../arm/mediatek/mediatek,mt8192-clock.yaml | 216
> > ++++++++++++++++++
> > .../mediatek/mediatek,mt8192-sys-clock.yaml | 66 ++++++
> > 2 files changed, 282 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > clock.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-
> > clock.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > clock.yaml
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > clock.yaml
> > new file mode 100644
> > index 000000000000..ce02c22c5d08
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > clock.yaml
> > @@ -0,0 +1,216 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: "
> > http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#
> > "
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > +
> > +title: MediaTek Functional Clock Controller for MT8192
> > +
> > +maintainers:
> > + - Chun-Jie Chen <chun-jie.chen at mediatek.com>
> > +
> > +description:
> > + The Mediatek functional clock controller provides various clocks
> > on MT8192.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - enum:
>
> You can simplify to just:
>
> compatible:
> enum:
> ...
>
> > + - mediatek,mt8192-scp_adsp
> > + - mediatek,mt8192-imp_iic_wrap_c
> > + - mediatek,mt8192-audsys
> > + - mediatek,mt8192-imp_iic_wrap_e
> > + - mediatek,mt8192-imp_iic_wrap_s
> > + - mediatek,mt8192-imp_iic_wrap_ws
> > + - mediatek,mt8192-imp_iic_wrap_w
> > + - mediatek,mt8192-imp_iic_wrap_n
> > + - mediatek,mt8192-msdc_top
> > + - mediatek,mt8192-msdc
> > + - mediatek,mt8192-mfgcfg
> > + - mediatek,mt8192-mmsys
> > + - mediatek,mt8192-imgsys
> > + - mediatek,mt8192-imgsys2
> > + - mediatek,mt8192-vdecsys_soc
> > + - mediatek,mt8192-vdecsys
> > + - mediatek,mt8192-vencsys
> > + - mediatek,mt8192-camsys
> > + - mediatek,mt8192-camsys_rawa
> > + - mediatek,mt8192-camsys_rawb
> > + - mediatek,mt8192-camsys_rawc
> > + - mediatek,mt8192-ipesys
> > + - mediatek,mt8192-mdpsys
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + '#clock-cells':
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + scp_adsp: clock-controller at 10720000 {
> > + compatible = "mediatek,mt8192-scp_adsp";
> > + reg = <0x10720000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + imp_iic_wrap_c: clock-controller at 11007000 {
> > + compatible = "mediatek,mt8192-imp_iic_wrap_c";
> > + reg = <0x11007000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + audsys: clock-controller at 11210000 {
> > + compatible = "mediatek,mt8192-audsys";
> > + reg = <0x11210000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + imp_iic_wrap_e: clock-controller at 11cb1000 {
> > + compatible = "mediatek,mt8192-imp_iic_wrap_e";
> > + reg = <0x11cb1000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + imp_iic_wrap_s: clock-controller at 11d03000 {
> > + compatible = "mediatek,mt8192-imp_iic_wrap_s";
> > + reg = <0x11d03000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + imp_iic_wrap_ws: clock-controller at 11d23000 {
> > + compatible = "mediatek,mt8192-imp_iic_wrap_ws";
> > + reg = <0x11d23000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + imp_iic_wrap_w: clock-controller at 11e01000 {
> > + compatible = "mediatek,mt8192-imp_iic_wrap_w";
> > + reg = <0x11e01000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + imp_iic_wrap_n: clock-controller at 11f02000 {
> > + compatible = "mediatek,mt8192-imp_iic_wrap_n";
> > + reg = <0x11f02000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + msdc_top: clock-controller at 11f10000 {
> > + compatible = "mediatek,mt8192-msdc_top";
> > + reg = <0x11f10000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + msdc: clock-controller at 11f60000 {
> > + compatible = "mediatek,mt8192-msdc";
> > + reg = <0x11f60000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + mfgcfg: clock-controller at 13fbf000 {
> > + compatible = "mediatek,mt8192-mfgcfg";
> > + reg = <0x13fbf000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + mmsys: clock-controller at 14000000 {
> > + compatible = "mediatek,mt8192-mmsys";
> > + reg = <0x14000000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + imgsys: clock-controller at 15020000 {
> > + compatible = "mediatek,mt8192-imgsys";
> > + reg = <0x15020000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + imgsys2: clock-controller at 15820000 {
> > + compatible = "mediatek,mt8192-imgsys2";
> > + reg = <0x15820000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + vdecsys_soc: clock-controller at 1600f000 {
> > + compatible = "mediatek,mt8192-vdecsys_soc";
> > + reg = <0x1600f000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + vdecsys: clock-controller at 1602f000 {
> > + compatible = "mediatek,mt8192-vdecsys";
> > + reg = <0x1602f000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + vencsys: clock-controller at 17000000 {
> > + compatible = "mediatek,mt8192-vencsys";
> > + reg = <0x17000000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + camsys: clock-controller at 1a000000 {
> > + compatible = "mediatek,mt8192-camsys";
> > + reg = <0x1a000000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + camsys_rawa: clock-controller at 1a04f000 {
> > + compatible = "mediatek,mt8192-camsys_rawa";
> > + reg = <0x1a04f000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + camsys_rawb: clock-controller at 1a06f000 {
> > + compatible = "mediatek,mt8192-camsys_rawb";
> > + reg = <0x1a06f000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + camsys_rawc: clock-controller at 1a08f000 {
> > + compatible = "mediatek,mt8192-camsys_rawc";
> > + reg = <0x1a08f000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + ipesys: clock-controller at 1b000000 {
> > + compatible = "mediatek,mt8192-ipesys";
> > + reg = <0x1b000000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + mdpsys: clock-controller at 1f000000 {
> > + compatible = "mediatek,mt8192-mdpsys";
> > + reg = <0x1f000000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > diff --git
> > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > new file mode 100644
> > index 000000000000..ececce3a1507
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-
> > sys-clock.yaml
> > @@ -0,0 +1,66 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: "
> > http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#
> > "
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > +
> > +title: MediaTek System Clock Controller for MT8192
> > +
> > +maintainers:
> > + - Chun-Jie Chen <chun-jie.chen at mediatek.com>
> > +
> > +description:
> > + The Mediatek system clock controller provides various clocks and
> > system configuration
> > + like reset and bus protection on MT8192.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
>
> And here, drop the 'oneOf'.
>
> With that,
>
> Reviewed-by: Rob Herring <robh at kernel.org>
>
Thanks for your comment, i will fix it in next patch.
Best Regards,
Chun-Jie
> > + - enum:
> > + - mediatek,mt8192-topckgen
> > + - mediatek,mt8192-infracfg
> > + - mediatek,mt8192-pericfg
> > + - mediatek,mt8192-apmixedsys
> > + - const: syscon
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + '#clock-cells':
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + topckgen: syscon at 10000000 {
> > + compatible = "mediatek,mt8192-topckgen", "syscon";
> > + reg = <0x10000000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + infracfg: syscon at 10001000 {
> > + compatible = "mediatek,mt8192-infracfg", "syscon";
> > + reg = <0x10001000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + pericfg: syscon at 10003000 {
> > + compatible = "mediatek,mt8192-pericfg", "syscon";
> > + reg = <0x10003000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + - |
> > + apmixedsys: syscon at 1000c000 {
> > + compatible = "mediatek,mt8192-apmixedsys", "syscon";
> > + reg = <0x1000c000 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > --
> > 2.18.0
> >
> >
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