[PATCH 06/27] arm64: dts: mt8195: add clock controllers
Tinghan Shen
tinghan.shen at mediatek.com
Tue Jun 15 10:32:12 PDT 2021
From: Weiyi Lu <weiyi.lu at mediatek.com>
Add clock controller nodes for SoC mt8195
Signed-off-by: Weiyi Lu <weiyi.lu at mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 215 ++++++++++++++++++++++-
1 file changed, 213 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 965445d07e92..7946a13fcbc3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
+#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
@@ -275,8 +276,14 @@
};
};
- infracfg: syscon at 10001000 {
- compatible = "mediatek,mt8195-infracfg", "syscon", "simple-mfd";
+ topckgen: syscon at 10000000 {
+ compatible = "mediatek,mt8195-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg_ao: infracfg_ao at 10001000 {
+ compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
@@ -315,6 +322,12 @@
reg = <0 0x10007000 0 0x100>;
};
+ apmixedsys: syscon at 1000c000 {
+ compatible = "mediatek,mt8195-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
systimer: timer at 10017000 {
compatible = "mediatek,mt8195-timer", "mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x1000>;
@@ -349,6 +362,30 @@
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC_D10>;
};
+ nnasys: syscon at 10211000 {
+ compatible = "mediatek,mt8195-nnasys", "syscon";
+ reg = <0 0x10211000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ scp_adsp: syscon at 10720000 {
+ compatible = "mediatek,mt8195-scp_adsp", "syscon";
+ reg = <0 0x10720000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ audsys: syscon at 10890000 {
+ compatible = "mediatek,mt8195-audsys", "syscon";
+ reg = <0 0x10890000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ audsys_src: syscon at 108a0000 {
+ compatible = "mediatek,mt8195-audsys_src", "syscon";
+ reg = <0 0x108a0000 0 0x2000>;
+ #clock-cells = <1>;
+ };
+
uart0: serial at 11001100 {
compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
reg = <0 0x11001100 0 0x100>;
@@ -411,6 +448,12 @@
status = "disabled";
};
+ pericfg_ao: syscon at 11003000 {
+ compatible = "mediatek,mt8195-pericfg_ao", "syscon";
+ reg = <0 0x11003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
mmc0: mmc at 11230000 {
compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
reg = <0 0x11230000 0 0x10000>,
@@ -472,6 +515,18 @@
};
};
+ imp_iic_wrap_s: syscon at 11d03000 {
+ compatible = "mediatek,mt8195-imp_iic_wrap_s", "syscon";
+ reg = <0 0x11d03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imp_iic_wrap_w: syscon at 11e05000 {
+ compatible = "mediatek,mt8195-imp_iic_wrap_w", "syscon";
+ reg = <0 0x11e05000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
u3phy1: t-phy at 11e30000 {
compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
#address-cells = <1>;
@@ -524,5 +579,161 @@
#phy-cells = <0>;
status = "disabled";
};
+
+ mfgcfg: syscon at 13fbf000 {
+ compatible = "mediatek,mt8195-mfgcfg", "syscon";
+ reg = <0 0x13fbf000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vppsys0: syscon at 14000000 {
+ compatible = "mediatek,mt8195-vppsys0", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys: syscon at 14e00000 {
+ compatible = "mediatek,mt8195-wpesys", "syscon";
+ reg = <0 0x14e00000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys_vpp0: syscon at 14e02000 {
+ compatible = "mediatek,mt8195-wpesys_vpp0", "syscon";
+ reg = <0 0x14e02000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys_vpp1: syscon at 14e03000 {
+ compatible = "mediatek,mt8195-wpesys_vpp1", "syscon";
+ reg = <0 0x14e03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vppsys1: syscon at 14f00000 {
+ compatible = "mediatek,mt8195-vppsys1", "syscon";
+ reg = <0 0x14f00000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: syscon at 15000000 {
+ compatible = "mediatek,mt8195-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_dip_top: syscon at 15110000 {
+ compatible = "mediatek,mt8195-imgsys1_dip_top", "syscon";
+ reg = <0 0x15110000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_dip_nr: syscon at 15130000 {
+ compatible = "mediatek,mt8195-imgsys1_dip_nr", "syscon";
+ reg = <0 0x15130000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_wpe: syscon at 15220000 {
+ compatible = "mediatek,mt8195-imgsys1_wpe", "syscon";
+ reg = <0 0x15220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipesys: syscon at 15330000 {
+ compatible = "mediatek,mt8195-ipesys", "syscon";
+ reg = <0 0x15330000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: syscon at 16000000 {
+ compatible = "mediatek,mt8195-camsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawa: syscon at 1604f000 {
+ compatible = "mediatek,mt8195-camsys_rawa", "syscon";
+ reg = <0 0x1604f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_yuva: syscon at 1606f000 {
+ compatible = "mediatek,mt8195-camsys_yuva", "syscon";
+ reg = <0 0x1606f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawb: syscon at 1608f000 {
+ compatible = "mediatek,mt8195-camsys_rawb", "syscon";
+ reg = <0 0x1608f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_yuvb: syscon at 160af000 {
+ compatible = "mediatek,mt8195-camsys_yuvb", "syscon";
+ reg = <0 0x160af000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_mraw: syscon at 16140000 {
+ compatible = "mediatek,mt8195-camsys_mraw", "syscon";
+ reg = <0 0x16140000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ccusys: syscon at 17200000 {
+ compatible = "mediatek,mt8195-ccusys", "syscon";
+ reg = <0 0x17200000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_soc: syscon at 1800f000 {
+ compatible = "mediatek,mt8195-vdecsys_soc", "syscon";
+ reg = <0 0x1800f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: syscon at 1802f000 {
+ compatible = "mediatek,mt8195-vdecsys", "syscon";
+ reg = <0 0x1802f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_core1: syscon at 1803f000 {
+ compatible = "mediatek,mt8195-vdecsys_core1", "syscon";
+ reg = <0 0x1803f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apusys_pll: syscon at 190f3000 {
+ compatible = "mediatek,mt8195-apusys_pll", "syscon";
+ reg = <0 0x190f3000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: syscon at 1a000000 {
+ compatible = "mediatek,mt8195-vencsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys_core1: syscon at 1b000000 {
+ compatible = "mediatek,mt8195-vencsys_core1", "syscon";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdosys0: syscon at 1c01a000 {
+ compatible = "mediatek,mt8195-vdosys0", "syscon";
+ reg = <0 0x1c01a000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdosys1: syscon at 1c100000 {
+ compatible = "mediatek,mt8195-vdosys1", "syscon";
+ reg = <0 0x1c100000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
};
--
2.18.0
More information about the Linux-mediatek
mailing list