[PATCH v1 09/17] drm/mediatek: add OVL support multi-layer
CK Hu
ck.hu at mediatek.com
Tue Jul 6 22:43:34 PDT 2021
Hi, Jason:
On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote:
> Add datapath_con settings to support multi-layer output.
What is multi-layer output? Why we need this?
>
> Signed-off-by: jason-jh.lin <jason-jh.lin at mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 7504e86b167a..95fd5e00eb91 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -18,14 +18,17 @@
> #include "mtk_drm_ddp_comp.h"
>
> #define DISP_REG_OVL_INTEN 0x0004
> -#define OVL_FME_CPL_INT BIT(1)
> +#define OVL_FME_CPL_INT BIT(1)
> #define DISP_REG_OVL_INTSTA 0x0008
> #define DISP_REG_OVL_EN 0x000c
> #define DISP_REG_OVL_RST 0x0014
> #define DISP_REG_OVL_ROI_SIZE 0x0020
> #define DISP_REG_OVL_DATAPATH_CON 0x0024
> -#define OVL_LAYER_SMI_ID_EN BIT(0)
> -#define OVL_BGCLR_SEL_IN BIT(2)
> +#define OVL_LAYER_SMI_ID_EN BIT(0)
> +#define OVL_BGCLR_SEL_IN BIT(2)
> +#define OVL_GCLAST_EN BIT(24)
> +#define OVL_HDR_GCLAST_EN BIT(25)
> +#define OVL_OUTPUT_CLAMP BIT(26)
> #define DISP_REG_OVL_ROI_BGCLR 0x0028
> #define DISP_REG_OVL_SRC_CON 0x002c
> #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n))
> @@ -222,6 +225,7 @@ void mtk_ovl_layer_on(struct device *dev, unsigned int idx,
> unsigned int gmc_thrshd_l;
> unsigned int gmc_thrshd_h;
> unsigned int gmc_value;
> + unsigned int datapatch_con;
> struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
>
> mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
> @@ -237,6 +241,11 @@ void mtk_ovl_layer_on(struct device *dev, unsigned int idx,
> gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
> mtk_ddp_write(cmdq_pkt, gmc_value,
> &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));
> +
> + datapatch_con = OVL_GCLAST_EN | OVL_HDR_GCLAST_EN | OVL_OUTPUT_CLAMP;
> + mtk_ddp_write_mask(cmdq_pkt, datapatch_con, &ovl->cmdq_reg, ovl->regs,
> + DISP_REG_OVL_DATAPATH_CON, datapatch_con);
For mt8173 or other SoC, this does not turn on. Now you turn on this,
would this influence other SoC?
Regards,
CK
> +
> mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,
> DISP_REG_OVL_SRC_CON, BIT(idx));
> }
More information about the Linux-mediatek
mailing list