[PATCH v3, 03/15] arm64: dts: mt8192: add display node

[Yongqiang Niu]

add display node

Signed-off-by: Yongqiang Niu <yongqiang.niu at mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 +++++++++++++++++++++++++++++++
 1 file changed, 134 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e12e024..dcf9fdf 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -15,6 +15,11 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		ovl2-2l2 = &ovl_2l2;
+		rdma4 = &rdma4;
+	};
+
 	clk26m: oscillator0 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -508,5 +513,134 @@
 			#size-cells = <0>;
 			status = "disabled";
 		};
+		
+		mmsys: syscon at 14000000 {
+			compatible = "mediatek,mt8192-mmsys", "syscon";
+			reg = <0 0x14000000 0 0x1000>;
+			//mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
+			//	 <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
+			//mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+                mutex: mutex at 14001000 {
+			compatible = "mediatek,mt8192-disp-mutex";
+			reg = <0 0x14001000 0 0x1000>;
+			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+			//clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
+			//mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+			//		      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
+		};
+
+		ovl0: ovl at 14005000 {
+			compatible = "mediatek,mt8192-disp-ovl";
+			reg = <0 0x14005000 0 0x1000>;
+			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+			//clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			//iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			//mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+		};
+
+		ovl_2l0: ovl at 14006000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14006000 0 0x1000>;
+			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			//clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+			//iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>;
+			//mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+		};
+
+		rdma0: rdma at 14007000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14007000 0 0x1000>;
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+			//clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+			//iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+			//mediatek,larb = <&larb0>;
+			//mediatek,rdma-fifo-size = <5120>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			//mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
+		};
+
+		color0: color at 14009000 {
+			compatible = "mediatek,mt8192-disp-color",
+				     "mediatek,mt8173-disp-color";
+			reg = <0 0x14009000 0 0x1000>;
+			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			//clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+			//mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+		};
+
+		ccorr0: ccorr at 1400a000 {
+			compatible = "mediatek,mt8192-disp-ccorr";
+			reg = <0 0x1400a000 0 0x1000>;
+			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			//clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+			//mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
+		};
+
+		aal0: aal at 1400b000 {
+			compatible = "mediatek,mt8192-disp-aal";
+			reg = <0 0x1400b000 0 0x1000>;
+			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			//clocks = <&mmsys CLK_MM_DISP_AAL0>;
+			//mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
+		};
+
+		gamma0: gamma at 1400c000 {
+			compatible = "mediatek,mt8183-disp-gamma",
+				     "mediatek,mt8192-disp-gamma";
+			reg = <0 0x1400c000 0 0x1000>;
+			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			//clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+			//mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+		};
+
+		postmask0: postmask at 1400d000 {
+			compatible = "mediatek,mt8192-disp-postmask";
+			reg = <0 0x1400d000 0 0x1000>;
+			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			//clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+			//mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+		};
+
+		dither0: dither at 1400e000 {
+			compatible = "mediatek,mt8192-disp-dither",
+				     "mediatek,mt8183-disp-dither";
+			reg = <0 0x1400e000 0 0x1000>;
+			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			//clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+			//mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+		};
+
+		ovl_2l2: ovl at 14014000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14014000 0 0x1000>;
+			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			//clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+			//iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+			//	 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+			//mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
+		};
+
+		rdma4: rdma at 14015000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14015000 0 0x1000>;
+			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			//clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+			//iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+			//mediatek,rdma-fifo-size = <2048>;
+			//mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+		};
 	};
 };
-- 
1.8.1.1.dirty