[RESEND PATCH v2] PCI: mediatek: Delay 100ms to wait power and clock to become stable

[qizhong.cheng]

On Thu, 2021-12-09 at 14:00 +0100, Pali Rohár wrote:
> On Thursday 09 December 2021 19:51:03 qizhong.cheng wrote:
> > On Wed, 2021-12-08 at 11:18 +0100, Pali Rohár wrote:
> > > On Wednesday 08 December 2021 14:07:57 qizhong.cheng wrote:
> > > > On Tue, 2021-12-07 at 22:12 -0600, Bjorn Helgaas wrote:
> > > > > On Tue, Dec 07, 2021 at 10:00:43PM +0100, Mark Ketteni
> > > > > 
> > > > > > > On Tue, Dec 07, 2021 at 04:41:53PM +0800, qizhong cheng
> > > > > > > wrote:
> > > > > > > > Described in PCIe CEM specification sections 2.2
> > > > > > > > (PERST#
> > > > > > > > Signal) and
> > > > > > > > 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of
> > > > > > > > PERST#
> > > > > > > > should
> > > > > > > > be delayed 100ms (TPVPERL) for the power and clock to
> > > > > > > > become
> > > > > > > > stable.
> > > > > > > > 
> > > > > > > > Signed-off-by: qizhong cheng <
> > > > > > > > qizhong.cheng at mediatek.com>
> > > > > > > > Acked-by: Pali Rohár <pali at kernel.org>
> > > > > > > 
> > > > > > > ...
> > > > 

> > > Hello! About month ago I was investigating correct order of steps
> > > and
> > > I
> > > wrote email about it, please look at it:
> > > 
> > 
> > 
https://lore.kernel.org/linux-pci/20211022183808.jdeo7vntnagqkg7g@pali/
> > 
> > Hi Pali,
> > 
> > Thanks for your investigating.
> > Modify the code to refer to your steps as following(please correct
> > me
> > if I'm wrong):
> > 1) pcie_assert_reset();
> > 2) pcie_power_on();
> > 3) pcie_setup_refclk();
> > 4) msleep(100);
> > 5) pcie_deassert_reset();
> > 6) polling_link_active_bit();
> > 7) msleep(100);
> 
> If I understood it correctly then above steps should be OK.
> ...

> > > 
> > > > > > >   - Does either apple or mediatek support speeds greater
> > > > > > > than
> > > > > > > 5
> > > > > > > GT/s,
> > > > > > >     and if so, shouldn't we start the sec 6.6.1 100ms
> > > > > > > delay
> > > > > > > *after*
> > > > > > >     Link training completes?
> > > > > > 
> > > > > > The Apple hardware advertises support for 8 GT/s, but all
> > > > > > the
> > > > > > devices
> > > > > > integrated on the Mac mini support only 2.5 GT/s or 5 GT/s.
> > > > > 
> > > > > 

Hi Bjorn and Pali,

Thanks for your review.

The hardware RC device corresponding to this version of driver is only
supports Gen1/Gen2, and the speed is not greater than 5GT/s. Adding
"delay 100ms" after link training is redundant for the entire boot
process. So, the "delay 100ms" after link training will not be added.

Also, based on the previous suggestion, I will change the subject
content.

Thanks