[v4 4/5] soc: mediatek: pm-domains: Move power status offset to power domain data

[Chen-Yu Tsai]

Hi,

On Mon, Aug 23, 2021 at 5:25 PM Chun-Jie Chen
<chun-jie.chen at mediatek.com> wrote:
>
> MT8195 has more than 32 power domains so it needs
> two set of pwr_sta and pwr_sta2nd registers,
> so move the register offset from soc data into power domain data.
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen at mediatek.com>
> Reviewed-by: Enric Balletbo i Serra <enric.balletbo at collabora.com>
> ---
>  drivers/soc/mediatek/mt8167-pm-domains.h | 16 +++++++--
>  drivers/soc/mediatek/mt8173-pm-domains.h | 22 ++++++++++--
>  drivers/soc/mediatek/mt8183-pm-domains.h | 32 +++++++++++++++--
>  drivers/soc/mediatek/mt8192-pm-domains.h | 44 ++++++++++++++++++++++--
>  drivers/soc/mediatek/mtk-pm-domains.c    |  4 +--
>  drivers/soc/mediatek/mtk-pm-domains.h    |  4 +--
>  6 files changed, 110 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8167-pm-domains.h b/drivers/soc/mediatek/mt8167-pm-domains.h
> index 15559ddf26e4..4d6c32759606 100644
> --- a/drivers/soc/mediatek/mt8167-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8167-pm-domains.h

[...]

> @@ -69,6 +83,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
>                 .name = "mfg_async",
>                 .sta_mask = PWR_STATUS_MFG_ASYNC,
>                 .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> +               .pwr_sta_offs = SPM_PWR_STATUS,
> +               .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
>                 .sram_pdn_bits = GENMASK(11, 8),
>                 .sram_pdn_ack_bits = 0,
>         },

This hunk no longer applies due to

    http://git.kernel.org/matthias.bgg/c/114956518c85f4e93c298749b35b46b2e78a2ec9

ChenYu