[PATCH v6 4/7] drm/mediatek: adjust to the alphabetic order for mediatek-drm
Jason-JH Lin
jason-jh.lin at mediatek.com
Wed Aug 11 09:23:46 PDT 2021
Hi CK,
On Mon, 2021-08-09 at 22:34 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin <jason-jh.lin at mediatek.com> 於 2021年8月6日 週五 上午4:52寫道：
> >
> > 1. Adjust to the alphabetic order for the define, function, struct
> > and array in mediatek-drm driver
> > 2. Remove the unsed define in mtk_drm_ddp_comp.c
>
> Separate the 2nd part to another patch.
OK, I'll separate them.
>
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin at mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 180 +++++++++-------
> > ----
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 22 +--
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 76 ++++-----
> > 3 files changed, 133 insertions(+), 145 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 75bc00e17fc4..328ee19f931e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -20,50 +20,36 @@
> > #include "mtk_drm_ddp_comp.h"
> > #include "mtk_drm_crtc.h"
> >
> > -#define DISP_OD_EN 0x0000
> > -#define DISP_OD_INTEN 0x0008
> > -#define DISP_OD_INTSTA 0x000c
> > -#define DISP_OD_CFG 0x0020
> > -#define DISP_OD_SIZE 0x0030
> > -#define DISP_DITHER_5 0x0114
> > -#define DISP_DITHER_7 0x011c
> > -#define DISP_DITHER_15 0x013c
> > -#define DISP_DITHER_16 0x0140
> > -
> > -#define DISP_REG_UFO_START 0x0000
> > -
> > -#define DISP_AAL_EN 0x0000
> > -#define DISP_AAL_SIZE 0x0030
> > +#define DISP_REG_AAL_EN 0x0000
> > +#define AAL_EN BIT(0)
> > +#define DISP_REG_AAL_SIZE 0x0030
> >
> > -#define DISP_DITHER_EN 0x0000
> > +#define DISP_REG_DITHER_EN 0x0000
>
> I think we should not change the register name just for alphabetic
> order. We list the register in the order of its address.
> If you have another reason to change register name, add another patch
> to do this.
>
> Regards,
> Chun-Kuang.
I think using DISP_REG prifix can identify the macro of register offset
and register value.
So I'll revert the changing of register name in this alphabetic order
patch and send this into another patch.
Regards,
Jason-JH.Lin
>
> > #define DITHER_EN BIT(0)
> > -#define DISP_DITHER_CFG 0x0020
> > +#define DISP_REG_DITHER_CFG 0x0020
> > #define DITHER_RELAY_MODE BIT(0)
> > #define DITHER_ENGINE_EN BIT(1)
> > -#define DISP_DITHER_SIZE 0x0030
> > -
> > -#define LUT_10BIT_MASK 0x03ff
> > -
> > -#define OD_RELAYMODE BIT(0)
> > -
> > -#define UFO_BYPASS BIT(2)
> > -
> > -#define AAL_EN BIT(0)
> > -
> > #define DISP_DITHERING BIT(2)
> > +#define DISP_REG_DITHER_SIZE 0x0030
> > +#define DISP_REG_DITHER_5 0x0114
> > +#define DISP_REG_DITHER_7 0x011c
> > +#define DISP_REG_DITHER_15 0x013c
> > #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
> > -#define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24)
> > #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
> > -#define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16)
> > #define DITHER_NEW_BIT_MODE BIT(0)
> > +#define DISP_REG_DITHER_16 0x0140
> > #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
> > -#define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24)
> > #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
> > -#define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16)
> > #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
> > -#define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8)
> > #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
> > -#define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
> > +
> > +#define DISP_REG_OD_EN 0x0000
> > +#define DISP_REG_OD_CFG 0x0020
> > +#define OD_RELAYMODE BIT(0)
> > +#define DISP_REG_OD_SIZE 0x0030
> > +
> > +#define DISP_REG_UFO_START 0x0000
> > +#define UFO_BYPASS BIT(2)
> >
> > struct mtk_ddp_comp_dev {
> > struct clk *clk;
> > @@ -116,20 +102,6 @@ void mtk_ddp_write_mask(struct cmdq_pkt
> > *cmdq_pkt, unsigned int value,
> > #endif
> > }
> >
> > -static int mtk_ddp_clk_enable(struct device *dev)
> > -{
> > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > - return clk_prepare_enable(priv->clk);
> > -}
> > -
> > -static void mtk_ddp_clk_disable(struct device *dev)
> > -{
> > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > - clk_disable_unprepare(priv->clk);
> > -}
> > -
> > void mtk_dither_set_common(void __iomem *regs, struct
> > cmdq_client_reg *cmdq_reg,
> > unsigned int bpc, unsigned int cfg,
> > unsigned int dither_en, struct cmdq_pkt
> > *cmdq_pkt)
> > @@ -139,55 +111,35 @@ void mtk_dither_set_common(void __iomem
> > *regs, struct cmdq_client_reg *cmdq_reg,
> > return;
> >
> > if (bpc >= MTK_MIN_BPC) {
> > - mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_DITHER_5);
> > - mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_DITHER_7);
> > + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_REG_DITHER_5);
> > + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs,
> > DISP_REG_DITHER_7);
> > mtk_ddp_write(cmdq_pkt,
> > DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC -
> > bpc) |
> > DITHER_ADD_LSHIFT_R(MTK_MAX_BPC -
> > bpc) |
> > DITHER_NEW_BIT_MODE,
> > - cmdq_reg, regs, DISP_DITHER_15);
> > + cmdq_reg, regs, DISP_REG_DITHER_15);
> > mtk_ddp_write(cmdq_pkt,
> > DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC -
> > bpc) |
> > DITHER_ADD_LSHIFT_B(MTK_MAX_BPC -
> > bpc) |
> > DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC -
> > bpc) |
> > DITHER_ADD_LSHIFT_G(MTK_MAX_BPC -
> > bpc),
> > - cmdq_reg, regs, DISP_DITHER_16);
> > + cmdq_reg, regs, DISP_REG_DITHER_16);
> > mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs,
> > cfg);
> > }
> > }
> >
> > -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > - unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> > -{
> > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > - mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > cfg,
> > - DISP_DITHERING, cmdq_pkt);
> > -}
> > -
> > -static void mtk_od_config(struct device *dev, unsigned int w,
> > - unsigned int h, unsigned int vrefresh,
> > - unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > -{
> > - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > - mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_OD_SIZE);
> > - mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg,
> > priv->regs, DISP_OD_CFG);
> > - mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt);
> > -}
> > -
> > -static void mtk_od_start(struct device *dev)
> > +static int mtk_ddp_clk_enable(struct device *dev)
> > {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >
> > - writel(1, priv->regs + DISP_OD_EN);
> > + return clk_prepare_enable(priv->clk);
> > }
> >
> > -static void mtk_ufoe_start(struct device *dev)
> > +static void mtk_ddp_clk_disable(struct device *dev)
> > {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >
> > - writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> > + clk_disable_unprepare(priv->clk);
> > }
> >
> > static void mtk_aal_config(struct device *dev, unsigned int w,
> > @@ -196,7 +148,7 @@ static void mtk_aal_config(struct device *dev,
> > unsigned int w,
> > {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >
> > - mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_AAL_SIZE);
> > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_AAL_SIZE);
> > }
> >
> > static void mtk_aal_gamma_set(struct device *dev, struct
> > drm_crtc_state *state)
> > @@ -210,14 +162,14 @@ static void mtk_aal_start(struct device *dev)
> > {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >
> > - writel(AAL_EN, priv->regs + DISP_AAL_EN);
> > + writel(AAL_EN, priv->regs + DISP_REG_AAL_EN);
> > }
> >
> > static void mtk_aal_stop(struct device *dev)
> > {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >
> > - writel_relaxed(0x0, priv->regs + DISP_AAL_EN);
> > + writel_relaxed(0x0, priv->regs + DISP_REG_AAL_EN);
> > }
> >
> > static void mtk_dither_config(struct device *dev, unsigned int w,
> > @@ -226,9 +178,11 @@ static void mtk_dither_config(struct device
> > *dev, unsigned int w,
> > {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs, DISP_DITHER_SIZE);
> > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg,
> > priv->regs, DISP_DITHER_CFG);
> > - mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > DISP_DITHER_CFG,
> > + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > + DISP_REG_DITHER_SIZE);
> > + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg,
> > priv->regs,
> > + DISP_REG_DITHER_CFG);
> > + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > DISP_REG_DITHER_CFG,
> > DITHER_ENGINE_EN, cmdq_pkt);
> > }
> >
> > @@ -236,14 +190,48 @@ static void mtk_dither_start(struct device
> > *dev)
> > {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >
> > - writel(DITHER_EN, priv->regs + DISP_DITHER_EN);
> > + writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN);
> > }
> >
> > static void mtk_dither_stop(struct device *dev)
> > {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >
> > - writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
> > + writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN);
> > +}
> > +
> > +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> > + unsigned int cfg, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > cfg,
> > + DISP_DITHERING, cmdq_pkt);
> > +}
> > +
> > +static void mtk_od_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt
> > *cmdq_pkt)
> > +{
> > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv-
> > >regs, DISP_REG_OD_SIZE);
> > + mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg,
> > priv->regs, DISP_REG_OD_CFG);
> > + mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt);
> > +}
> > +
> > +static void mtk_od_start(struct device *dev)
> > +{
> > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > + writel(1, priv->regs + DISP_REG_OD_EN);
> > +}
> > +
> > +static void mtk_ufoe_start(struct device *dev)
> > +{
> > + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +
> > + writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
> > }
> >
> > static const struct mtk_ddp_comp_funcs ddp_aal = {
> > @@ -340,22 +328,22 @@ static const struct mtk_ddp_comp_funcs
> > ddp_ufoe = {
> > };
> >
> > static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX]
> > = {
> > + [MTK_DISP_AAL] = "aal",
> > + [MTK_DISP_BLS] = "bls",
> > + [MTK_DISP_CCORR] = "ccorr",
> > + [MTK_DISP_COLOR] = "color",
> > + [MTK_DISP_DITHER] = "dither",
> > + [MTK_DISP_GAMMA] = "gamma",
> > + [MTK_DISP_MUTEX] = "mutex",
> > + [MTK_DISP_OD] = "od",
> > [MTK_DISP_OVL] = "ovl",
> > [MTK_DISP_OVL_2L] = "ovl-2l",
> > + [MTK_DISP_PWM] = "pwm",
> > [MTK_DISP_RDMA] = "rdma",
> > - [MTK_DISP_WDMA] = "wdma",
> > - [MTK_DISP_COLOR] = "color",
> > - [MTK_DISP_CCORR] = "ccorr",
> > - [MTK_DISP_AAL] = "aal",
> > - [MTK_DISP_GAMMA] = "gamma",
> > - [MTK_DISP_DITHER] = "dither",
> > [MTK_DISP_UFOE] = "ufoe",
> > - [MTK_DSI] = "dsi",
> > + [MTK_DISP_WDMA] = "wdma",
> > [MTK_DPI] = "dpi",
> > - [MTK_DISP_PWM] = "pwm",
> > - [MTK_DISP_MUTEX] = "mutex",
> > - [MTK_DISP_OD] = "od",
> > - [MTK_DISP_BLS] = "bls",
> > + [MTK_DSI] = "dsi",
> > };
> >
> > struct mtk_ddp_comp_match {
> > @@ -509,12 +497,12 @@ int mtk_ddp_comp_init(struct device_node
> > *node, struct mtk_ddp_comp *comp,
> > type == MTK_DISP_CCORR ||
> > type == MTK_DISP_COLOR ||
> > type == MTK_DISP_GAMMA ||
> > - type == MTK_DPI ||
> > - type == MTK_DSI ||
> > type == MTK_DISP_OVL ||
> > type == MTK_DISP_OVL_2L ||
> > type == MTK_DISP_PWM ||
> > - type == MTK_DISP_RDMA)
> > + type == MTK_DISP_RDMA ||
> > + type == MTK_DPI ||
> > + type == MTK_DSI)
> > return 0;
> >
> > priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index bb914d976cf5..d317b944df66 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -18,22 +18,22 @@ struct mtk_plane_state;
> > struct drm_crtc_state;
> >
> > enum mtk_ddp_comp_type {
> > - MTK_DISP_OVL,
> > - MTK_DISP_OVL_2L,
> > - MTK_DISP_RDMA,
> > - MTK_DISP_WDMA,
> > - MTK_DISP_COLOR,
> > + MTK_DISP_AAL,
> > + MTK_DISP_BLS,
> > MTK_DISP_CCORR,
> > + MTK_DISP_COLOR,
> > MTK_DISP_DITHER,
> > - MTK_DISP_AAL,
> > MTK_DISP_GAMMA,
> > - MTK_DISP_UFOE,
> > - MTK_DSI,
> > - MTK_DPI,
> > - MTK_DISP_PWM,
> > MTK_DISP_MUTEX,
> > MTK_DISP_OD,
> > - MTK_DISP_BLS,
> > + MTK_DISP_OVL,
> > + MTK_DISP_OVL_2L,
> > + MTK_DISP_PWM,
> > + MTK_DISP_RDMA,
> > + MTK_DISP_UFOE,
> > + MTK_DISP_WDMA,
> > + MTK_DPI,
> > + MTK_DSI,
> > MTK_DDP_COMP_TYPE_MAX,
> > };
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index b46bdb8985da..a95dc1006b82 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -396,50 +396,20 @@ static const struct component_master_ops
> > mtk_drm_ops = {
> > };
> >
> > static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> > - { .compatible = "mediatek,mt2701-disp-ovl",
> > - .data = (void *)MTK_DISP_OVL },
> > - { .compatible = "mediatek,mt8173-disp-ovl",
> > - .data = (void *)MTK_DISP_OVL },
> > - { .compatible = "mediatek,mt8183-disp-ovl",
> > - .data = (void *)MTK_DISP_OVL },
> > - { .compatible = "mediatek,mt8183-disp-ovl-2l",
> > - .data = (void *)MTK_DISP_OVL_2L },
> > - { .compatible = "mediatek,mt2701-disp-rdma",
> > - .data = (void *)MTK_DISP_RDMA },
> > - { .compatible = "mediatek,mt8173-disp-rdma",
> > - .data = (void *)MTK_DISP_RDMA },
> > - { .compatible = "mediatek,mt8183-disp-rdma",
> > - .data = (void *)MTK_DISP_RDMA },
> > - { .compatible = "mediatek,mt8173-disp-wdma",
> > - .data = (void *)MTK_DISP_WDMA },
> > + { .compatible = "mediatek,mt8173-disp-aal",
> > + .data = (void *)MTK_DISP_AAL},
> > { .compatible = "mediatek,mt8183-disp-ccorr",
> > .data = (void *)MTK_DISP_CCORR },
> > { .compatible = "mediatek,mt2701-disp-color",
> > .data = (void *)MTK_DISP_COLOR },
> > { .compatible = "mediatek,mt8173-disp-color",
> > .data = (void *)MTK_DISP_COLOR },
> > - { .compatible = "mediatek,mt8173-disp-aal",
> > - .data = (void *)MTK_DISP_AAL},
> > + { .compatible = "mediatek,mt8183-disp-dither",
> > + .data = (void *)MTK_DISP_DITHER },
> > { .compatible = "mediatek,mt8173-disp-gamma",
> > .data = (void *)MTK_DISP_GAMMA, },
> > { .compatible = "mediatek,mt8183-disp-gamma",
> > .data = (void *)MTK_DISP_GAMMA, },
> > - { .compatible = "mediatek,mt8183-disp-dither",
> > - .data = (void *)MTK_DISP_DITHER },
> > - { .compatible = "mediatek,mt8173-disp-ufoe",
> > - .data = (void *)MTK_DISP_UFOE },
> > - { .compatible = "mediatek,mt2701-dsi",
> > - .data = (void *)MTK_DSI },
> > - { .compatible = "mediatek,mt8173-dsi",
> > - .data = (void *)MTK_DSI },
> > - { .compatible = "mediatek,mt8183-dsi",
> > - .data = (void *)MTK_DSI },
> > - { .compatible = "mediatek,mt2701-dpi",
> > - .data = (void *)MTK_DPI },
> > - { .compatible = "mediatek,mt8173-dpi",
> > - .data = (void *)MTK_DPI },
> > - { .compatible = "mediatek,mt8183-dpi",
> > - .data = (void *)MTK_DPI },
> > { .compatible = "mediatek,mt2701-disp-mutex",
> > .data = (void *)MTK_DISP_MUTEX },
> > { .compatible = "mediatek,mt2712-disp-mutex",
> > @@ -448,12 +418,42 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_MUTEX },
> > { .compatible = "mediatek,mt8183-disp-mutex",
> > .data = (void *)MTK_DISP_MUTEX },
> > + { .compatible = "mediatek,mt8173-disp-od",
> > + .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt2701-disp-ovl",
> > + .data = (void *)MTK_DISP_OVL },
> > + { .compatible = "mediatek,mt8173-disp-ovl",
> > + .data = (void *)MTK_DISP_OVL },
> > + { .compatible = "mediatek,mt8183-disp-ovl",
> > + .data = (void *)MTK_DISP_OVL },
> > + { .compatible = "mediatek,mt8183-disp-ovl-2l",
> > + .data = (void *)MTK_DISP_OVL_2L },
> > { .compatible = "mediatek,mt2701-disp-pwm",
> > .data = (void *)MTK_DISP_BLS },
> > { .compatible = "mediatek,mt8173-disp-pwm",
> > .data = (void *)MTK_DISP_PWM },
> > - { .compatible = "mediatek,mt8173-disp-od",
> > - .data = (void *)MTK_DISP_OD },
> > + { .compatible = "mediatek,mt2701-disp-rdma",
> > + .data = (void *)MTK_DISP_RDMA },
> > + { .compatible = "mediatek,mt8173-disp-rdma",
> > + .data = (void *)MTK_DISP_RDMA },
> > + { .compatible = "mediatek,mt8183-disp-rdma",
> > + .data = (void *)MTK_DISP_RDMA },
> > + { .compatible = "mediatek,mt8173-disp-ufoe",
> > + .data = (void *)MTK_DISP_UFOE },
> > + { .compatible = "mediatek,mt8173-disp-wdma",
> > + .data = (void *)MTK_DISP_WDMA },
> > + { .compatible = "mediatek,mt2701-dpi",
> > + .data = (void *)MTK_DPI },
> > + { .compatible = "mediatek,mt8173-dpi",
> > + .data = (void *)MTK_DPI },
> > + { .compatible = "mediatek,mt8183-dpi",
> > + .data = (void *)MTK_DPI },
> > + { .compatible = "mediatek,mt2701-dsi",
> > + .data = (void *)MTK_DSI },
> > + { .compatible = "mediatek,mt8173-dsi",
> > + .data = (void *)MTK_DSI },
> > + { .compatible = "mediatek,mt8183-dsi",
> > + .data = (void *)MTK_DSI },
> > { }
> > };
> >
> > @@ -542,8 +542,8 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> > comp_type == MTK_DISP_OVL ||
> > comp_type == MTK_DISP_OVL_2L ||
> > comp_type == MTK_DISP_RDMA ||
> > - comp_type == MTK_DSI ||
> > - comp_type == MTK_DPI) {
> > + comp_type == MTK_DPI ||
> > + comp_type == MTK_DSI) {
> > dev_info(dev, "Adding component match for
> > %pOF\n",
> > node);
> > drm_of_component_match_add(dev, &match,
> > compare_of,
> > --
> > 2.18.0
> >
--
Jason-JH Lin <jason-jh.lin at mediatek.com>
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