[v6 1/2] arm64: dts: mediatek: Add mt8192 clock controllers
Matthias Brugger
matthias.bgg at gmail.com
Thu Aug 5 08:43:20 PDT 2021
On 27/07/2021 04:32, Chun-Jie Chen wrote:
> Add clock controller nodes for SoC mt8192
>
> Signed-off-by: Weiyi Lu <weiyi.lu at mediatek.com>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen at mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 163 +++++++++++++++++++++++
> 1 file changed, 163 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 9757138a8bbd..c7c7d4e017ae 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -5,6 +5,7 @@
> */
>
> /dts-v1/;
> +#include <dt-bindings/clock/mt8192-clk.h>
I'd need a stable branch from Stephen to be able to take this one. Otherwise
we'll need to wait for v5.15-rc1 to be published before I can take them without
compile errors.
Regards,
Matthias
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
> @@ -257,6 +258,24 @@
> };
> };
>
> + topckgen: syscon at 10000000 {
> + compatible = "mediatek,mt8192-topckgen", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon at 10001000 {
> + compatible = "mediatek,mt8192-infracfg", "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + pericfg: syscon at 10003000 {
> + compatible = "mediatek,mt8192-pericfg", "syscon";
> + reg = <0 0x10003000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> pio: pinctrl at 10005000 {
> compatible = "mediatek,mt8192-pinctrl";
> reg = <0 0x10005000 0 0x1000>,
> @@ -282,6 +301,12 @@
> #interrupt-cells = <2>;
> };
>
> + apmixedsys: syscon at 1000c000 {
> + compatible = "mediatek,mt8192-apmixedsys", "syscon";
> + reg = <0 0x1000c000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> systimer: timer at 10017000 {
> compatible = "mediatek,mt8192-timer",
> "mediatek,mt6765-timer";
> @@ -291,6 +316,12 @@
> clock-names = "clk13m";
> };
>
> + scp_adsp: clock-controller at 10720000 {
> + compatible = "mediatek,mt8192-scp_adsp";
> + reg = <0 0x10720000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> uart0: serial at 11002000 {
> compatible = "mediatek,mt8192-uart",
> "mediatek,mt6577-uart";
> @@ -311,6 +342,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_c: clock-controller at 11007000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_c";
> + reg = <0 0x11007000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> spi0: spi at 1100a000 {
> compatible = "mediatek,mt8192-spi",
> "mediatek,mt6765-spi";
> @@ -436,6 +473,12 @@
> status = "disable";
> };
>
> + audsys: clock-controller at 11210000 {
> + compatible = "mediatek,mt8192-audsys", "syscon";
> + reg = <0 0x11210000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c3: i2c3 at 11cb0000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11cb0000 0 0x1000>,
> @@ -449,6 +492,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_e: clock-controller at 11cb1000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_e";
> + reg = <0 0x11cb1000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c7: i2c7 at 11d00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11d00000 0 0x1000>,
> @@ -488,6 +537,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_s: clock-controller at 11d03000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_s";
> + reg = <0 0x11d03000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c1: i2c1 at 11d20000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11d20000 0 0x1000>,
> @@ -527,6 +582,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_ws: clock-controller at 11d23000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_ws";
> + reg = <0 0x11d23000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c5: i2c5 at 11e00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11e00000 0 0x1000>,
> @@ -540,6 +601,12 @@
> status = "disabled";
> };
>
> + imp_iic_wrap_w: clock-controller at 11e01000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_w";
> + reg = <0 0x11e01000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> i2c0: i2c0 at 11f00000 {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11f00000 0 0x1000>,
> @@ -565,5 +632,101 @@
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + imp_iic_wrap_n: clock-controller at 11f02000 {
> + compatible = "mediatek,mt8192-imp_iic_wrap_n";
> + reg = <0 0x11f02000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + msdc_top: clock-controller at 11f10000 {
> + compatible = "mediatek,mt8192-msdc_top";
> + reg = <0 0x11f10000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + msdc: clock-controller at 11f60000 {
> + compatible = "mediatek,mt8192-msdc";
> + reg = <0 0x11f60000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mfgcfg: clock-controller at 13fbf000 {
> + compatible = "mediatek,mt8192-mfgcfg";
> + reg = <0 0x13fbf000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mmsys: syscon at 14000000 {
> + compatible = "mediatek,mt8192-mmsys", "syscon";
> + reg = <0 0x14000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + imgsys: clock-controller at 15020000 {
> + compatible = "mediatek,mt8192-imgsys";
> + reg = <0 0x15020000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + imgsys2: clock-controller at 15820000 {
> + compatible = "mediatek,mt8192-imgsys2";
> + reg = <0 0x15820000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vdecsys_soc: clock-controller at 1600f000 {
> + compatible = "mediatek,mt8192-vdecsys_soc";
> + reg = <0 0x1600f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vdecsys: clock-controller at 1602f000 {
> + compatible = "mediatek,mt8192-vdecsys";
> + reg = <0 0x1602f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vencsys: clock-controller at 17000000 {
> + compatible = "mediatek,mt8192-vencsys";
> + reg = <0 0x17000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys: clock-controller at 1a000000 {
> + compatible = "mediatek,mt8192-camsys";
> + reg = <0 0x1a000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys_rawa: clock-controller at 1a04f000 {
> + compatible = "mediatek,mt8192-camsys_rawa";
> + reg = <0 0x1a04f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys_rawb: clock-controller at 1a06f000 {
> + compatible = "mediatek,mt8192-camsys_rawb";
> + reg = <0 0x1a06f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys_rawc: clock-controller at 1a08f000 {
> + compatible = "mediatek,mt8192-camsys_rawc";
> + reg = <0 0x1a08f000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + ipesys: clock-controller at 1b000000 {
> + compatible = "mediatek,mt8192-ipesys";
> + reg = <0 0x1b000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mdpsys: clock-controller at 1f000000 {
> + compatible = "mediatek,mt8192-mdpsys";
> + reg = <0 0x1f000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> };
> };
>
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