Support 1 of N SPI interrupt for interrupt distribution

[Hanks Chen]

*** BLURB HERE ***
The GICv3 supports 1 of N selection of SPI interrupts.
When the GICD_IROUTERn.Interrupt_Routing_Mode == 1, the GIC selects
the appropriate core for a SPI.

Actually, dispatch the interrupt by hardware Interrupt Control Unit
is more efficient than irqbalance of software logic
and no need to implement software contoller to decide the targeted CPU
on various platform.

In order to reduce interrupt latency, all interrupts are targeted to
each online CPU defaultly by 1 of N selection of SPI interrupts.
That is, SPI interrupts might be serviced simultaneously on different CPUs.

[default policy]
AS-IS (target to boot CPU)
       CPU0       CPU1       CPU2       CPU3
 29:     92          0          0          0     GICv3 141 Level   ttyS0

TO-BE (enable ARM_IRQ_TARGET_ALL)
       CPU0       CPU1       CPU2       CPU3
 29:     23         23         24         22     GICv3 141 Level   ttyS0


Hanks Chen (3):
  irqchip/gic: enable irq target all
  arm: disable irq on cpu shutdown flow
  arm64: disable irq on cpu shutdown flow

 arch/arm/kernel/smp.c              |  10 ++-
 arch/arm64/kernel/smp.c            |   9 ++-
 drivers/irqchip/Kconfig            |  12 ++++
 drivers/irqchip/irq-gic-v3.c       | 107 +++++++++++++++++++++--------
 include/linux/irqchip/arm-gic-v3.h |   1 +
 kernel/irq/cpuhotplug.c            |  22 ++++++
 kernel/irq/manage.c                |   7 ++
 7 files changed, 138 insertions(+), 30 deletions(-)

-- 
2.18.0