[PATCH v7 1/4] dt-bindings: pci: mediatek: Modified the Device tree bindings
Chuanjia Liu
chuanjia.liu at mediatek.com
Sun Nov 8 22:01:44 EST 2020
On Tue, 2020-11-03 at 16:56 -0600, Bjorn Helgaas wrote:
> Run "git log --oneline" and follow the convention, e.g.,
>
> dt-bindings: PCI: mediatek: ...
>
thanks for your comment, I will update to
dt-bindings: PCI: mediatek: Update the Device tree bindings
> On Thu, Oct 29, 2020 at 04:15:10PM +0800, Chuanjia Liu wrote:
> > Split the PCIe node and add pciecfg node to fix MSI issue.
>
> I assume "split" refers to the new yaml file? It's not really obvious
> how the two files are connected.
In mt2712 and mt7622,old DTS format is one PCIe controller have two slot.
In new DTS, split two independent PCIe controller and a pciecfg node.
I once added the "mediatek,pcie-cfg = <&pciecfg>" in PCIe node,
but Rob suggested that search for the node by compatible.so I remove it.
> Could this be done in two patches? One for the split and one for the
> MSI issue?
MSI issue is fixed when the PCIe node is separated. So I think this should be one patch.
> It'd be nice to say something more about the MSI issue.
The detailed description in patch 3/4, I will add description of the msi
issue in the next version of this patch.
Thanks again for your review.
>
> > Signed-off-by: Chuanjia Liu <chuanjia.liu at mediatek.com>
> > Acked-by: Ryder Lee <ryder.lee at mediatek.com>
> > ---
> > .../bindings/pci/mediatek-pcie-cfg.yaml | 39 ++++++
> > .../devicetree/bindings/pci/mediatek-pcie.txt | 129 +++++++++++-------
> > 2 files changed, 118 insertions(+), 50 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
> > new file mode 100644
> > index 000000000000..d3ecbcd032a2
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
> > @@ -0,0 +1,39 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek PCIECFG controller
> > +
> > +maintainers:
> > + - Chuanjia Liu <chuanjia.liu at mediatek.com>
> > + - Jianjun Wang <jianjun.wang at mediatek.com>
> > +
> > +description: |
> > + The MediaTek PCIECFG controller controls some feature about
> > + LTSSM, ASPM and so on.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,generic-pciecfg
> > + - const: syscon
> > +
> > + reg:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + pciecfg: pciecfg at 1a140000 {
> > + compatible = "mediatek,generic-pciecfg", "syscon";
> > + reg = <0x1a140000 0x1000>;
> > + };
> > +...
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
> > index 7468d666763a..c14a2745de37 100644
> > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
> > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
> > @@ -8,7 +8,7 @@ Required properties:
> > "mediatek,mt7623-pcie"
> > "mediatek,mt7629-pcie"
> > - device_type: Must be "pci"
> > -- reg: Base addresses and lengths of the PCIe subsys and root ports.
> > +- reg: Base addresses and lengths of the root ports.
> > - reg-names: Names of the above areas to use during resource lookup.
> > - #address-cells: Address representation for root ports (must be 3)
> > - #size-cells: Size representation for root ports (must be 2)
> > @@ -143,56 +143,71 @@ Examples for MT7623:
> >
> > Examples for MT2712:
> >
> > - pcie: pcie at 11700000 {
> > + pcie1: pcie at 112ff000 {
> > compatible = "mediatek,mt2712-pcie";
> > device_type = "pci";
> > - reg = <0 0x11700000 0 0x1000>,
> > - <0 0x112ff000 0 0x1000>;
> > - reg-names = "port0", "port1";
> > + reg = <0 0x112ff000 0 0x1000>;
> > + reg-names = "port1";
> > #address-cells = <3>;
> > #size-cells = <2>;
> > - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> > - clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
> > - <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
> > - <&pericfg CLK_PERI_PCIE0>,
> > + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "pcie_irq";
> > + clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
> > <&pericfg CLK_PERI_PCIE1>;
> > - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
> > - phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
> > - phy-names = "pcie-phy0", "pcie-phy1";
> > + clock-names = "sys_ck1", "ahb_ck1";
> > + phys = <&u3port1 PHY_TYPE_PCIE>;
> > + phy-names = "pcie-phy1";
> > bus-range = <0x00 0xff>;
> > - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
> > + ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
> >
> > - pcie0: pcie at 0,0 {
> > - reg = <0x0000 0 0 0 0>;
> > + slot1: pcie at 1,0 {
> > + reg = <0x0800 0 0 0 0>;
> > #address-cells = <3>;
> > #size-cells = <2>;
> > #interrupt-cells = <1>;
> > ranges;
> > interrupt-map-mask = <0 0 0 7>;
> > - interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> > - <0 0 0 2 &pcie_intc0 1>,
> > - <0 0 0 3 &pcie_intc0 2>,
> > - <0 0 0 4 &pcie_intc0 3>;
> > - pcie_intc0: interrupt-controller {
> > + interrupt-map = <0 0 0 1 &pcie_intc1 0>,
> > + <0 0 0 2 &pcie_intc1 1>,
> > + <0 0 0 3 &pcie_intc1 2>,
> > + <0 0 0 4 &pcie_intc1 3>;
> > + pcie_intc1: interrupt-controller {
> > interrupt-controller;
> > #address-cells = <0>;
> > #interrupt-cells = <1>;
> > };
> > };
> > + };
> >
> > - pcie1: pcie at 1,0 {
> > - reg = <0x0800 0 0 0 0>;
> > + pcie0: pcie at 11700000 {
> > + compatible = "mediatek,mt2712-pcie";
> > + device_type = "pci";
> > + reg = <0 0x11700000 0 0x1000>;
> > + reg-names = "port0";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "pcie_irq";
> > + clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
> > + <&pericfg CLK_PERI_PCIE0>;
> > + clock-names = "sys_ck0", "ahb_ck0";
> > + phys = <&u3port0 PHY_TYPE_PCIE>;
> > + phy-names = "pcie-phy0";
> > + bus-range = <0x00 0xff>;
> > + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
> > +
> > + slot0: pcie at 0,0 {
> > + reg = <0x0000 0 0 0 0>;
> > #address-cells = <3>;
> > #size-cells = <2>;
> > #interrupt-cells = <1>;
> > ranges;
> > interrupt-map-mask = <0 0 0 7>;
> > - interrupt-map = <0 0 0 1 &pcie_intc1 0>,
> > - <0 0 0 2 &pcie_intc1 1>,
> > - <0 0 0 3 &pcie_intc1 2>,
> > - <0 0 0 4 &pcie_intc1 3>;
> > - pcie_intc1: interrupt-controller {
> > + interrupt-map = <0 0 0 1 &pcie_intc0 0>,
> > + <0 0 0 2 &pcie_intc0 1>,
> > + <0 0 0 3 &pcie_intc0 2>,
> > + <0 0 0 4 &pcie_intc0 3>;
> > + pcie_intc0: interrupt-controller {
> > interrupt-controller;
> > #address-cells = <0>;
> > #interrupt-cells = <1>;
> > @@ -202,39 +217,29 @@ Examples for MT2712:
> >
> > Examples for MT7622:
> >
> > - pcie: pcie at 1a140000 {
> > + pcie0: pcie at 1a143000 {
> > compatible = "mediatek,mt7622-pcie";
> > device_type = "pci";
> > - reg = <0 0x1a140000 0 0x1000>,
> > - <0 0x1a143000 0 0x1000>,
> > - <0 0x1a145000 0 0x1000>;
> > - reg-names = "subsys", "port0", "port1";
> > + reg = <0 0x1a143000 0 0x1000>;
> > + reg-names = "port0";
> > #address-cells = <3>;
> > #size-cells = <2>;
> > - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
> > - <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
> > + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
> > + interrupt-names = "pcie_irq";
> > clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
> > - <&pciesys CLK_PCIE_P1_MAC_EN>,
> > <&pciesys CLK_PCIE_P0_AHB_EN>,
> > - <&pciesys CLK_PCIE_P1_AHB_EN>,
> > <&pciesys CLK_PCIE_P0_AUX_EN>,
> > - <&pciesys CLK_PCIE_P1_AUX_EN>,
> > <&pciesys CLK_PCIE_P0_AXI_EN>,
> > - <&pciesys CLK_PCIE_P1_AXI_EN>,
> > <&pciesys CLK_PCIE_P0_OBFF_EN>,
> > - <&pciesys CLK_PCIE_P1_OBFF_EN>,
> > - <&pciesys CLK_PCIE_P0_PIPE_EN>,
> > - <&pciesys CLK_PCIE_P1_PIPE_EN>;
> > - clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
> > - "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
> > - "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
> > - phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
> > - phy-names = "pcie-phy0", "pcie-phy1";
> > + <&pciesys CLK_PCIE_P0_PIPE_EN>;
> > + clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
> > + "axi_ck0", "obff_ck0", "pipe_ck0";
> > +
> > power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
> > bus-range = <0x00 0xff>;
> > - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
> > + ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
> >
> > - pcie0: pcie at 0,0 {
> > + slot0: pcie at 0,0 {
> > reg = <0x0000 0 0 0 0>;
> > #address-cells = <3>;
> > #size-cells = <2>;
> > @@ -251,8 +256,32 @@ Examples for MT7622:
> > #interrupt-cells = <1>;
> > };
> > };
> > + };
> > +
> > + pcie1: pcie at 1a145000 {
> > + compatible = "mediatek,mt7622-pcie";
> > + device_type = "pci";
> > + reg = <0 0x1a145000 0 0x1000>;
> > + reg-names = "port1";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
> > + interrupt-names = "pcie_irq";
> > + clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
> > + /* designer has connect RC1 with p0_ahb clock */
> > + <&pciesys CLK_PCIE_P0_AHB_EN>,
> > + <&pciesys CLK_PCIE_P1_AUX_EN>,
> > + <&pciesys CLK_PCIE_P1_AXI_EN>,
> > + <&pciesys CLK_PCIE_P1_OBFF_EN>,
> > + <&pciesys CLK_PCIE_P1_PIPE_EN>;
> > + clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
> > + "axi_ck1", "obff_ck1", "pipe_ck1";
> > +
> > + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
> > + bus-range = <0x00 0xff>;
> > + ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
> >
> > - pcie1: pcie at 1,0 {
> > + slot1: pcie at 1,0 {
> > reg = <0x0800 0 0 0 0>;
> > #address-cells = <3>;
> > #size-cells = <2>;
> > --
> > 2.18.0
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