[v3,2/3] PCI: mediatek: Add new generation controller support

[Jianjun Wang]

On Mon, 2020-09-28 at 10:32 +0200, Philipp Zabel wrote:
> Hi Jianjun,
> 
> On Sun, 2020-09-27 at 15:45 +0800, Jianjun Wang wrote:
> > MediaTek's PCIe host controller has three generation HWs, the new
> > generation HW is an individual bridge, it supoorts Gen3 speed and
> > up to 256 MSI interrupt numbers for multi-function devices.
> > 
> > Add support for new Gen3 controller which can be found on MT8192.
> > 
> > Signed-off-by: Jianjun Wang <jianjun.wang at mediatek.com>
> > Acked-by: Ryder Lee <ryder.lee at mediatek.com>
> > ---
> >  drivers/pci/controller/Kconfig              |   14 +
> >  drivers/pci/controller/Makefile             |    1 +
> >  drivers/pci/controller/pcie-mediatek-gen3.c | 1024 +++++++++++++++++++
> >  3 files changed, 1039 insertions(+)
> >  create mode 100644 drivers/pci/controller/pcie-mediatek-gen3.c
> > 
> [...]
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> > new file mode 100644
> > index 000000000000..ad69c789b24d
> > --- /dev/null
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -0,0 +1,1024 @@
> [...]
> > +static int mtk_pcie_power_up(struct mtk_pcie_port *port)
> > +{
> > +	struct device *dev = port->dev;
> > +	int err;
> > +
> > +	port->phy_reset = devm_reset_control_get_optional_exclusive(dev,
> > +								    "phy-rst");
> > +	if (IS_ERR(port->phy_reset))
> > +		return PTR_ERR(port->phy_reset);
> > +
> > +	reset_control_deassert(port->phy_reset);
> 
> In general, it is better to request all required resources before
> starting to activate the hardware.
> 
> > +
> > +	/* PHY power on and enable pipe clock */
> > +	port->phy = devm_phy_optional_get(dev, "pcie-phy");
> > +	if (IS_ERR(port->phy))
> > +		return PTR_ERR(port->phy);
> 
> For example, if the PHY driver is not loaded yet and this returns
> -EPROBE_DEFER, it was not useful to take the PHY out of reset above.
> Also, phy-rst is kept deasserted if this fails.
> 
> > +
> > +	err = phy_init(port->phy);
> > +	if (err) {
> > +		dev_notice(dev, "failed to initialize pcie phy\n");
> > +		return err;
> 
> phy-rst is kept deasserted if this fails.
> 
> > +	}
> > +
> > +	err = phy_power_on(port->phy);
> > +	if (err) {
> > +		dev_notice(dev, "failed to power on pcie phy\n");
> > +		goto err_phy_on;
> > +	}
> > +
> > +	port->mac_reset = devm_reset_control_get_optional_exclusive(dev,
> > +								    "mac-rst");
> > +	if (IS_ERR(port->mac_reset))
> > +		return PTR_ERR(port->mac_reset);
> 
> The PHY is not powered down if this fails.
> 
> > +
> > +	reset_control_deassert(port->mac_reset);
> > +
> > +	/* MAC power on and enable transaction layer clocks */
> > +	pm_runtime_enable(dev);
> > +	pm_runtime_get_sync(dev);
> > +
> > +	err = mtk_pcie_clk_init(port);
> > +	if (err) {
> > +		dev_notice(dev, "clock init failed\n");
> > +		goto err_clk_init;
> > +	}
> > +
> > +	return 0;
> > +
> > +err_clk_init:
> > +	pm_runtime_put_sync(dev);
> > +	pm_runtime_disable(dev);
> > +	reset_control_assert(port->mac_reset);
> > +	phy_power_off(port->phy);
> > +err_phy_on:
> > +	phy_exit(port->phy);
> > +	reset_control_assert(port->phy_reset);
> > +
> > +	return -EBUSY;
> > +}
> > +
> > +static void mtk_pcie_power_down(struct mtk_pcie_port *port)
> > +{
> > +	phy_power_off(port->phy);
> > +	phy_exit(port->phy);
> > +
> > +	clk_bulk_disable_unprepare(port->num_clks, port->clks);
> 
> In the power-up sequence clocks are enabled last, but here they are not
> disabled before the PHY is powered off. Is this on purpose?
> 
> > +
> > +	pm_runtime_put_sync(port->dev);
> > +	pm_runtime_disable(port->dev);
> 
> In the power-up error path, PHY and controller resets are asserted
> again, but here they are kept deasserted. Should they be asserted here
> as well?
> 
> regards
> Philipp

Hi Philipp,

Sorry for the late responding and thanks for your review, I will fix it
in the next version.

Thanks.