[PATCH v7 16/21] memory: mtk-smi: Add bus_sel for mt8183

Matthias Brugger matthias.bgg at gmail.com
Tue Jun 18 14:07:30 PDT 2019



On 18/06/2019 14:10, Yong Wu wrote:
> On Mon, 2019-06-17 at 18:23 +0200, Matthias Brugger wrote:
>>
>> On 10/06/2019 14:17, Yong Wu wrote:
>>> There are 2 mmu cells in a M4U HW. we could adjust some larbs entering
>>> mmu0 or mmu1 to balance the bandwidth via the smi-common register
>>> SMI_BUS_SEL(0x220)(Each larb occupy 2 bits).
>>>
>>> In mt8183, For better performance, we switch larb1/2/5/7 to enter
>>> mmu1 while the others still keep enter mmu0.
>>>
>>> In mt8173 and mt2712, we don't get the performance issue,
>>> Keep its default value(0x0), that means all the larbs enter mmu0.
>>>
>>> Note: smi gen1(mt2701/mt7623) don't have this bus_sel.
>>>
>>> And, the base of smi-common is completely different with smi_ao_base
>>> of gen1, thus I add new variable for that.
>>>
>>> CC: Matthias Brugger <matthias.bgg at gmail.com>
>>> Signed-off-by: Yong Wu <yong.wu at mediatek.com>
>>> Reviewed-by: Evan Green <evgreen at chromium.org>
>>> ---
>>>  drivers/memory/mtk-smi.c | 22 ++++++++++++++++++++--
>>>  1 file changed, 20 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
>>> index 9790801..08cf40d 100644
>>> --- a/drivers/memory/mtk-smi.c
>>> +++ b/drivers/memory/mtk-smi.c
>>> @@ -49,6 +49,12 @@
>>>  #define SMI_LARB_NONSEC_CON(id)	(0x380 + ((id) * 4))
>>>  #define F_MMU_EN		BIT(0)
>>>  
>>> +/* SMI COMMON */
>>> +#define SMI_BUS_SEL			0x220
>>> +#define SMI_BUS_LARB_SHIFT(larbid)	((larbid) << 1)
>>> +/* All are MMU0 defaultly. Only specialize mmu1 here. */
>>> +#define F_MMU1_LARB(larbid)		(0x1 << SMI_BUS_LARB_SHIFT(larbid))
>>> +
>>>  enum mtk_smi_gen {
>>>  	MTK_SMI_GEN1,
>>>  	MTK_SMI_GEN2
>>> @@ -57,6 +63,7 @@ enum mtk_smi_gen {
>>>  struct mtk_smi_common_plat {
>>>  	enum mtk_smi_gen gen;
>>>  	bool             has_gals;
>>> +	u32              bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
>>>  };
>>>  
>>>  struct mtk_smi_larb_gen {
>>> @@ -72,8 +79,8 @@ struct mtk_smi {
>>>  	struct clk			*clk_apb, *clk_smi;
>>>  	struct clk			*clk_gals0, *clk_gals1;
>>>  	struct clk			*clk_async; /*only needed by mt2701*/
>>> -	void __iomem			*smi_ao_base;
>>> -
>>> +	void __iomem			*smi_ao_base; /* only for gen1 */
>>> +	void __iomem			*base;	      /* only for gen2 */
>>
>> union {} maybe?
> 
> Yes. Thanks.
> 
> I will add it.
> 
>>
>>>  	const struct mtk_smi_common_plat *plat;
>>>  };
>>>  
>>> @@ -410,6 +417,8 @@ static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
>>>  static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
>>>  	.gen      = MTK_SMI_GEN2,
>>>  	.has_gals = true,
>>> +	.bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
>>> +		    F_MMU1_LARB(7),
>>>  };
>>>  
>>>  static const struct of_device_id mtk_smi_common_of_ids[] = {
>>> @@ -482,6 +491,11 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
>>>  		ret = clk_prepare_enable(common->clk_async);
>>>  		if (ret)
>>>  			return ret;
>>> +	} else {
>>> +		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> +		common->base = devm_ioremap_resource(dev, res);
>>> +		if (IS_ERR(common->base))
>>> +			return PTR_ERR(common->base);
>>
>> We must be backwards compatible with DT which does not have the base defined.
> 
> The smi-common node in the previous mt2712 and mt8173 also have the
> "reg" property even though they didn't use this base, Thus, It looks ok
> for all the cases.
> 

Correct, it is defined as a required property in the binding description so we
are good.
Sorry for the noise.

With the union added you can add:
Reviewed-by: Matthias Brugger <matthias.bgg at gmail.com>

>>
>> Regards,
>> Matthias
>>
>>>  	}
>>>  	pm_runtime_enable(dev);
>>>  	platform_set_drvdata(pdev, common);
>>> @@ -497,6 +511,7 @@ static int mtk_smi_common_remove(struct platform_device *pdev)
>>>  static int __maybe_unused mtk_smi_common_resume(struct device *dev)
>>>  {
>>>  	struct mtk_smi *common = dev_get_drvdata(dev);
>>> +	u32 bus_sel = common->plat->bus_sel;
>>>  	int ret;
>>>  
>>>  	ret = mtk_smi_clk_enable(common);
>>> @@ -504,6 +519,9 @@ static int __maybe_unused mtk_smi_common_resume(struct device *dev)
>>>  		dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
>>>  		return ret;
>>>  	}
>>> +
>>> +	if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
>>> +		writel(bus_sel, common->base + SMI_BUS_SEL);
>>>  	return 0;
>>>  }
>>>  
>>>
> 
> 



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