[PATCH 11/11] arm64: dts: mt2712: use non-empty ranges for usb-phy

Chunfeng Yun chunfeng.yun at mediatek.com
Fri Aug 23 00:00:18 PDT 2019


Use non-empty ranges for usb-phy to make the layout of
its registers clearer

Signed-off-by: Chunfeng Yun <chunfeng.yun at mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 36 +++++++++++------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 43307bad3f0d..37a6443b658e 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -698,29 +698,29 @@
 
 	u3phy0: usb-phy at 11290000 {
 		compatible = "mediatek,mt2712-u3phy";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x11290000 0x9000>;
 		status = "okay";
 
-		u2port0: usb-phy at 11290000 {
-			reg = <0 0x11290000 0 0x700>;
+		u2port0: usb-phy at 0 {
+			reg = <0x0 0x700>;
 			clocks = <&clk26m>;
 			clock-names = "ref";
 			#phy-cells = <1>;
 			status = "okay";
 		};
 
-		u2port1: usb-phy at 11298000 {
-			reg = <0 0x11298000 0 0x700>;
+		u2port1: usb-phy at 8000 {
+			reg = <0x8000 0x700>;
 			clocks = <&clk26m>;
 			clock-names = "ref";
 			#phy-cells = <1>;
 			status = "okay";
 		};
 
-		u3port0: usb-phy at 11298700 {
-			reg = <0 0x11298700 0 0x900>;
+		u3port0: usb-phy at 8700 {
+			reg = <0x8700 0x900>;
 			clocks = <&clk26m>;
 			clock-names = "ref";
 			#phy-cells = <1>;
@@ -761,29 +761,29 @@
 
 	u3phy1: usb-phy at 112e0000 {
 		compatible = "mediatek,mt2712-u3phy";
-		#address-cells = <2>;
-		#size-cells = <2>;
-		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0x112e0000 0x9000>;
 		status = "okay";
 
-		u2port2: usb-phy at 112e0000 {
-			reg = <0 0x112e0000 0 0x700>;
+		u2port2: usb-phy at 0 {
+			reg = <0x0 0x700>;
 			clocks = <&clk26m>;
 			clock-names = "ref";
 			#phy-cells = <1>;
 			status = "okay";
 		};
 
-		u2port3: usb-phy at 112e8000 {
-			reg = <0 0x112e8000 0 0x700>;
+		u2port3: usb-phy at 8000 {
+			reg = <0x8000 0x700>;
 			clocks = <&clk26m>;
 			clock-names = "ref";
 			#phy-cells = <1>;
 			status = "okay";
 		};
 
-		u3port1: usb-phy at 112e8700 {
-			reg = <0 0x112e8700 0 0x900>;
+		u3port1: usb-phy at 8700 {
+			reg = <0x8700 0x900>;
 			clocks = <&clk26m>;
 			clock-names = "ref";
 			#phy-cells = <1>;
-- 
2.23.0




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